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NJU6677 NJU6677 preliminary preliminary 88-common x 132-segment 88-common x 132-segment bit map lcd driver bit map lcd driver package outline package outline NJU6677cl NJU6677cl general description general description features features the NJU6677 is a bit map lcd driver to display graphics or charac- the NJU6677 is a bit map lcd driver to display graphics or charac- ters. it contains 15,840 bits display data ram, microprocessor inter- ters. it contains 15,840 bits display data ram, microprocessor inter- face circuits, instruction decoder, 132-segment and 88-common driv- face circuits, instruction decoder, 132-segment and 88-common driv- ers. ers. the bit image display data is transferred to the display data ram by the bit image display data is transferred to the display data ram by serial or 8-bit parallel interface. serial or 8-bit parallel interface. the NJU6677 displays 88 x 132 dots graphics or 8-character 5-line by the NJU6677 displays 88 x 132 dots graphics or 8-character 5-line by 16 x 16 dots character. 16 x 16 dots character. it oscillates by built-in osc circuit without any external components. it oscillates by built-in osc circuit without any external components. furthermore, the NJU6677 features partial display function which furthermore, the NJU6677 features partial display function which creates up to 2 blocks of active display area and optimizes duty cycle creates up to 2 blocks of active display area and optimizes duty cycle ratio. this function sets optimum boosted voltage by the combination ratio. this function sets optimum boosted voltage by the combination with both of programmable 5-time voltage booster circuit and 201- with both of programmable 5-time voltage booster circuit and 201- step electrical variable resistor. as result, it reduces the operating cur- step electrical variable resistor. as result, it reduces the operating cur- rent. rent. the operating voltage from 2.4v to 3.6v and low operating current are the operating voltage from 2.4v to 3.6v and low operating current are useful for small size battery operating items. useful for small size battery operating items. direct correspondence between display data ram and lcd pixel direct correspondence between display data ram and lcd pixel display data ram - 15,840 bits display data ram - 15,840 bits 220 lcd drivers - 88-common and 132-segment 220 lcd drivers - 88-common and 132-segment direct microprocessor interface for both of 68 and 80 type mpu direct microprocessor interface for both of 68 and 80 type mpu serial interface serial interface partial display function partial display function ( ( 2 blocks of active display area and automatic 2 blocks of active display area and automatic duty cycle ratio selection) duty cycle ratio selection) easy vertical scroll by the variable start line address and over size display data ram easy vertical scroll by the variable start line address and over size display data ram programmable bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10 bias programmable bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10 bias common driver order assignment by mask option common driver order assignment by mask option version version c c 0 0 to c to c 87 87 (pin name) (pin name) NJU6677a NJU6677a com com 0 0 to com to com 87 87 NJU6677b NJU6677b com com 87 87 to com to com 0 0 useful instruction set useful instruction set display data read/write, display on/off cont, inverse display, page address set, display data read/write, display on/off cont, inverse display, page address set, display start line set, partial display, bias select, column address set, status read, display start line set, partial display, bias select, column address set, status read, all on/off, voltage booster circuits multiple select(maximum 5-time), n-line inverse, all on/off, voltage booster circuits multiple select(maximum 5-time), n-line inverse, read modify write, power saving, adc select, etc. read modify write, power saving, adc select, etc. power supply circuits for lcd; programmable voltage booster circuits(5-time maximum), power supply circuits for lcd; programmable voltage booster circuits(5-time maximum), regulator, voltage follower x 4 regulator, voltage follower x 4 precision electrical variable resistance precision electrical variable resistance low power consumption low power consumption operating voltage operating voltage --- 2.4v to 3.6v --- 2.4v to 3.6v lcd driving voltage lcd driving voltage --- 6.0v to 18v --- 6.0v to 18v package outline package outline --- cof / tcp / bumped chip --- cof / tcp / bumped chip c-mos technology c-mos technology jul.10.2000 jul.10.2000 ver.2.1 ver.2.1
NJU6677 NJU6677 pad location pad location chip center chip center : x=0um,y=0um : x=0um,y=0um chip size chip size : x=8.31mm,y=2.93mm : x=8.31mm,y=2.93mm chip thickness chip thickness : 675um : 675um + + 30um 30um bump size bump size : 45um x 83um : 45um x 83um pad pitch pad pitch : 60um(min) : 60um(min) bump height bump height : 15um typ. : 15um typ. bump material bump material : au : au c 1 - t 1 t 2 a 0 c s 1 c 4 3 c 8 7 v 2 v 3 v 4 v 5 v r v d d v o u t c 2 - c 2 + c 4 + c 3 + c 3 - c 4 - c 1 + s e l 6 8 p / s v s s v d d d u m m y 0 v d d c 0 c 4 4 s 1 s 1 3 0 s 1 2 9 o s c 1 v s s d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 r d w r y x v 1 r e s s 2 o s c 2 d u m m y 1 d u m m y 2 d u m m y 3 d u m m y 4 s 0 s 1 3 1
NJU6677 NJU6677 terminal description terminal description chip size 8.31x2.93mm (chip center x=0um,y=0um) chip size 8.31x2.93mm (chip center x=0um,y=0um) pad no. terminal x= um y= um pad no. terminal x= um y= um 1 dummy0 -3884.0 -1305.0 51 c 6 3995.0 -958.1 2 v dd -3179.2 -1305.0 52 c 7 3995.0 -898.1 3 p/s -3014.1 -1305.0 53 c 8 3995.0 -838.1 4 sel68 -2793.7 -1305.0 54 c 9 3995.0 -778.1 5 res -2557.3 -1305.0 55 c 10 3995.0 -718.1 6 v ss -2400.1 -1305.0 56 c 11 3995.0 -658.1 7 t 2 -2242.9 -1305.0 57 c 12 3995.0 -598.1 8 t 1 -2007.3 -1305.0 58 c 13 3995.0 -538.1 9 osc 1 -1786.9 -1305.0 59 c 14 3995.0 -478.1 10 osc 2 -1550.5 -1305.0 60 c 15 3995.0 -418.1 11 cs -1330.1 -1305.0 61 c 16 3995.0 -358.1 12 a0 -1093.7 -1305.0 62 c 17 3995.0 -298.1 13 wr -873.3 -1305.0 63 c 18 3995.0 -238.1 14 rd -636.9 -1305.0 64 c 19 3995.0 -178.1 15 d 0 -400.2 -1305.0 65 c 20 3995.0 -118.1 16 d 1 -179.8 -1305.0 66 c 21 3995.0 -58.1 17 d 2 40.6 -1305.0 67 c 22 3995.0 1.9 18 d 3 261.0 -1305.0 68 c 23 3995.0 61.9 19 d 4 481.4 -1305.0 69 c 24 3995.0 121.9 20 d 5 701.8 -1305.0 70 c 25 3995.0 181.9 21 d 6(scl) 922.2 -1305.0 71 c 26 3995.0 241.9 22 d 7(si) 1142.6 -1305.0 72 c 27 3995.0 301.9 23 v ss 1300.1 -1305.0 73 c 28 3995.0 361.9 24 v out 1370.1 -1305.0 74 c 29 3995.0 421.9 25 c4 + 1466.0 -1305.0 75 c 30 3995.0 481.9 26 c4 - 1614.8 -1305.0 76 c 31 3995.0 541.9 27 c3 + 1674.8 -1305.0 77 c 32 3995.0 601.9 28 c3 - 1823.6 -1305.0 78 c 33 3995.0 661.9 29 c2 + 1883.6 -1305.0 79 c 34 3995.0 721.9 30 c2 - 2032.4 -1305.0 80 c 35 3995.0 781.9 31 c1 + 2092.4 -1305.0 81 c 36 3995.0 841.9 32 c1 - 2241.2 -1305.0 82 c 37 3995.0 901.9 33 v dd 2311.2 -1305.0 83 c 38 3995.0 961.9 34 vr 2491.2 -1305.0 84 c 39 3995.0 1021.9 35 v 5 2561.2 -1305.0 85 c 40 3995.0 1081.9 36 v 4 2631.2 -1305.0 86 c 41 3995.0 1141.9 37 v 3 2701.2 -1305.0 87 c 42 3995.0 1201.9 38 v 2 2771.2 -1305.0 88 c 43 3995.0 1261.9 39 v 1 2841.2 -1305.0 89 s 0 3995.0 1321.9 40 v dd 2911.2 -1305.0 90 s 1 3870.0 1305.0 41 dummy1 3119.2 -1305.0 91 s 2 3810.0 1305.0 42 dummy2 3179.2 -1305.0 92 s 3 3750.0 1305.0 43 dummy3 3239.2 -1305.0 93 s 4 3690.0 1305.0 44 dummy4 3884.0 -1305.0 94 s 5 3630.0 1305.0 45 c 0 3995.0 -1318.1 95 s 6 3570.0 1305.0 46 c 1 3995.0 -1258.1 96 s 7 3510.0 1305.0 47 c 2 3995.0 -1198.1 97 s 8 3450.0 1305.0 48 c 3 3995.0 -1138.1 98 s 9 3390.0 1305.0 49 c 4 3995.0 -1078.1 99 s 10 3330.0 1305.0 50 c 5 3995.0 -1018.1 100 s 11 3270.0 1305.0
NJU6677 NJU6677 pad no. terminal x= um y= um pad no. terminal x= um y= um 101 s 12 3210.0 1305.0 151 s 62 210.0 1305.0 102 s 13 3150.0 1305.0 152 s 63 150.0 1305.0 103 s 14 3090.0 1305.0 153 s 64 90.0 1305.0 104 s 15 3030.0 1305.0 154 s 65 30.0 1305.0 105 s 16 2970.0 1305.0 155 s 66 -30.0 1305.0 106 s 17 2910.0 1305.0 156 s 67 -90.0 1305.0 107 s 18 2850.0 1305.0 157 s 68 -150.0 1305.0 108 s 19 2790.0 1305.0 158 s 69 -210.0 1305.0 109 s 20 2730.0 1305.0 159 s 70 -270.0 1305.0 110 s 21 2670.0 1305.0 160 s 71 -330.0 1305.0 111 s 22 2610.0 1305.0 161 s 72 -390.0 1305.0 112 s 23 2550.0 1305.0 162 s 73 -450.0 1305.0 113 s 24 2490.0 1305.0 163 s 74 -510.0 1305.0 114 s 25 2430.0 1305.0 164 s 75 -570.0 1305.0 115 s 26 2370.0 1305.0 165 s 76 -630.0 1305.0 116 s 27 2310.0 1305.0 166 s 77 -690.0 1305.0 117 s 28 2250.0 1305.0 167 s 78 -750.0 1305.0 118 s 29 2190.0 1305.0 168 s 79 -810.0 1305.0 119 s 30 2130.0 1305.0 169 s 80 -870.0 1305.0 120 s 31 2070.0 1305.0 170 s 81 -930.0 1305.0 121 s 32 2010.0 1305.0 171 s 82 -990.0 1305.0 122 s 33 1950.0 1305.0 172 s 83 -1050.0 1305.0 123 s 34 1890.0 1305.0 173 s 84 -1110.0 1305.0 124 s 35 1830.0 1305.0 174 s 85 -1170.0 1305.0 125 s 36 1770.0 1305.0 175 s 86 -1230.0 1305.0 126 s 37 1710.0 1305.0 176 s 87 -1290.0 1305.0 127 s 38 1650.0 1305.0 177 s 88 -1350.0 1305.0 128 s 39 1590.0 1305.0 178 s 89 -1410.0 1305.0 129 s 40 1530.0 1305.0 179 s 90 -1470.0 1305.0 130 s 41 1470.0 1305.0 180 s 91 -1530.0 1305.0 131 s 42 1410.0 1305.0 181 s 92 -1590.0 1305.0 132 s 43 1350.0 1305.0 182 s 93 -1650.0 1305.0 133 s 44 1290.0 1305.0 183 s 94 -1710.0 1305.0 134 s 45 1230.0 1305.0 184 s 95 -1770.0 1305.0 135 s 46 1170.0 1305.0 185 s 96 -1830.0 1305.0 136 s 47 1110.0 1305.0 186 s 97 -1890.0 1305.0 137 s 48 1050.0 1305.0 187 s 98 -1950.0 1305.0 138 s 49 990.0 1305.0 188 s 99 -2010.0 1305.0 139 s 50 930.0 1305.0 189 s 100 -2070.0 1305.0 140 s 51 870.0 1305.0 190 s 101 -2130.0 1305.0 141 s 52 810.0 1305.0 191 s 102 -2190.0 1305.0 142 s 53 750.0 1305.0 192 s 103 -2250.0 1305.0 143 s 54 690.0 1305.0 193 s 104 -2310.0 1305.0 144 s 55 630.0 1305.0 194 s 105 -2370.0 1305.0 145 s 56 570.0 1305.0 195 s 106 -2430.0 1305.0 146 s 57 510.0 1305.0 196 s 107 -2490.0 1305.0 147 s 58 450.0 1305.0 197 s 108 -2550.0 1305.0 148 s 59 390.0 1305.0 198 s 109 -2610.0 1305.0 149 s 60 330.0 1305.0 199 s 110 -2670.0 1305.0 150 s 61 270.0 1305.0 200 s 111 -2730.0 1305.0
NJU6677 NJU6677 pad no. terminal x= um y= um pad no. terminal x= um y= um 201 s 112 -2790.0 1305.0 251 c 57 -3995.0 -538.1 202 s 113 -2850.0 1305.0 252 c 56 -3995.0 -598.1 203 s 114 -2910.0 1305.0 253 c 55 -3995.0 -658.1 204 s 115 -2970.0 1305.0 254 c 54 -3995.0 -718.1 205 s 116 -3030.0 1305.0 255 c 53 -3995.0 -778.1 206 s 117 -3090.0 1305.0 256 c 52 -3995.0 -838.1 207 s 118 -3150.0 1305.0 257 c 51 -3995.0 -898.1 208 s 119 -3210.0 1305.0 258 c 50 -3995.0 -958.1 209 s 120 -3270.0 1305.0 259 c 49 -3995.0 -1018.1 210 s 121 -3330.0 1305.0 260 c 48 -3995.0 -1078.1 211 s 122 -3390.0 1305.0 261 c 47 -3995.0 -1138.1 212 s 123 -3450.0 1305.0 262 c 46 -3995.0 -1198.1 213 s 124 -3510.0 1305.0 263 c 45 -3995.0 -1258.1 214 s 125 -3570.0 1305.0 264 c 44 -3995.0 -1318.1 215 s 126 -3630.0 1305.0 216 s 127 -3690.0 1305.0 217 s 128 -3750.0 1305.0 218 s 129 -3810.0 1305.0 219 s 130 -3870.0 1305.0 220 s 131 -3995.0 1321.9 221 c 87 -3995.0 1261.9 222 c 86 -3995.0 1201.9 223 c 85 -3995.0 1141.9 224 c 84 -3995.0 1081.9 225 c 83 -3995.0 1021.9 226 c 82 -3995.0 961.9 227 c 81 -3995.0 901.9 228 c 80 -3995.0 841.9 229 c 79 -3995.0 781.9 230 c 78 -3995.0 721.9 231 c 77 -3995.0 661.9 232 c 76 -3995.0 601.9 233 c 75 -3995.0 541.9 234 c 74 -3995.0 481.9 235 c 73 -3995.0 421.9 236 c 72 -3995.0 361.9 237 c 71 -3995.0 301.9 238 c 70 -3995.0 241.9 239 c 69 -3995.0 181.9 240 c 68 -3995.0 121.9 241 c 67 -3995.0 61.9 242 c 66 -3995.0 1.9 243 c 65 -3995.0 -58.1 244 c 64 -3995.0 -118.1 245 c 63 -3995.0 -178.1 246 c 62 -3995.0 -238.1 247 c 61 -3995.0 -298.1 248 c 60 -3995.0 -358.1 249 c 59 -3995.0 -418.1 250 c 58 -3995.0 -478.1
NJU6677 NJU6677 block diagram block diagram c 0 c 4 3 s 0 s 1 3 1 c 8 7 c 4 4 v s s v d d v 1 t o v 5 v r t 1 , t 2 1 2 0 x 1 3 2 c s a 0 r d w r s e l 6 8 p / s r e s o s c 1 d 0 t o d 7 ( s i , s c l ) 5 c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - o s c 2 c o m d r i v e r s e g d r i v e r c o m d r i v e r s h i f t r e g i s t e r d i s p l a y d a t a l a t c h v o l t a g e g e n e r a t o r r o w a d d r e s s d e c o d e r o u t p u t a s s i g n m e n t r e g i s t e r p a g e a d d r e s s r e g i s t e r i / o b u f f e r i n s t r u c t i o n d e c o d e r r e s e t s t a t u s c u l u m n a d d r e s s r e g i s t e r c u l u m n a d d r e s s c o u n t e r m u l t i p l e x e r b f d i s p l a y t i m i n g g e n e r a t o r b u s h o l d e r o s c . l i n e a d d r e s s d e c o d e r l i n e c o u n t e r s h i f t r e g i s t e r c o m s e g g e n e r a t o r t i m i n g m p u i n t e r f a c e i n t e r n a l b u s d i s p l a y d a t a r a m c u l u m n a d d r e s s d e c o d e r s t a r t l i n e r e g i s t e r
NJU6677 NJU6677 no. symbol i/o f u n c t i o n 1,41 to 44 dummy0 to dummy4 dummy terminals. these terminals are insulated. 2,33,40 v dd power v dd =+3v 6,23 v ss gnd v ss =0v 39, 38, 37, 36, 35 v 1 v 2 v 3 v 4 v 5 power lcd driving voltage supplying terminal. when the internal voltage booster is not used, supply each level of lcd driving voltage from outside with following relation. vdd>v1>v2>v3>v4>v5 when the internal power supply is on, the internal circuits generate and supply following lcd bias voltage from v 1 to v 4 terminals. (v lcd =v dd -v 5 ) 31,32, 29,30, 27,28, 25,26 c1 + ,c1 - c2 + ,c2 - c3 + ,c3 - c4 + ,c4 - o step up capacitor connecting terminals. voltage booster circuit (maximum 5-time) 24 v out o step up voltage output terminal. connect the step up capacitor between this terminal and v ss . 34 vr i voltage adjust terminal. v 5 level is adjusted by external bleeder resistance connecting between v dd and v 5 terminal. 8, 7 t 1 t 2 i lcd bias voltage control terminals. ( *:don't care) 15 to 22 d 0 to d 7 (si) (scl) i/o p/s="h" : tri-state bi-directional data i/o terminal in 8-bit parallel operation. p/s="l" : d 7 =serial data input terminal. d 6 =serial data clock signal input terminal. data from si is loaded at the rising edge of scl and latched as the parallel data at 8th rising edge of scl. 12 a0 i connect to the address bus of mpu. the data on the d 0 to d 7 is distinguished between display data and instruction by status of a0. 5 res i reset terminal. when the res terminal goes to "l", the initialization is performed. reset operation is executing during "l" state of res. 11 cs i chip select terminal. data input/output are available during cs ="l". terminal description terminal description bias v1 v2 v3 v4 1/4bias v5+3/4vlcd v5+2/4vlcd v5+2/4vlcd v5+1/4vlcd 1/5bias v5+4/5vlcd v5+3/5vlcd v5+2/5vlcd v5+1/5vlcd 1/6bias v5+5/6vlcd v5+4/6vlcd v5+2/6vlcd v5+1/6vlcd 1/7bias v5+6/7vlcd v5+5/7vlcd v5+2/7vlcd v5+1/7vlcd 1/8bias v5+7/8vlcd v5+6/8vlcd v5+2/8vlcd v5+1/8vlcd 1/9bias v5+8/9vlcd v5+7/9vlcd v5+2/9vlcd v5+1/9vlcd 1/10bias v5+9/10vlcd v5+8/10vlcd v5+2/10vlcd v5+1/10vlcd t 1 t 2 voltage booster cir. voltage adj. v/f cir. l * available available available h l not avail. available available h h not avail. not avail. available a0 h l distin. display data instruction = = = = = = = = = =
NJU6677 NJU6677 no symbol i/o f u n c t i o n 14 rd(e) i rd signal of 80 type mpu input terminal. active "l" during this signal is "l" , d 0 to d 7 terminals are output. enable signal of 68 type mpu input terminal. active "h" 13 wr(rw) i connect to the 80 type mpu wr signal. actie "l". the data on the data bus input syncronizing the rise edge of this signal. the read/write control signal of 68 type mpu input terminal. 4 sel68 i mpu interface type selection terminal. 3 p/s i serial or parallel interface selection terminal. ram data and status read operation do not work in mode of the serial interface. in case of the serial interface (p/s="l"),rd and wr must be fixed "h" or "l", and d 0 to d 5 are high impedance. 9, 10 osc 1 osc 2 i system clock input terminal for maker testing.(this terminal should be open) for external clock operation, the clock shoud be input to osc1 terminal. 45 to 88 c 0 to c 43 o lcd driving signal output terminals. segmet output terminals:s 0 to s 131 common output terminals:c 0 to c 87 segment output terminal the following output voltages are selected by the combination of fr and data in the ram.(non of the n-line inverse functions) common output terminal the following output voltages are selected by the combination of fr and status of common. 89 to 220 s 0 to s 131 o 264 to 221 c 44 to c 87 o sel68 h l state 68 type 80 type p/s chip select data/command data read/write serial clock "h" cs a d 0 to d 7 rd,wr - "l" cs a0 si(d 7 ) write only scl(d 6 ) scan data fr output voltage h h v 5 l v dd l h v 1 l v 4 ram data fr output voltage normal reverse h h v dd v 2 l v 5 v 3 l h v 2 v dd l v 3 v 5 r/w h l state read write
NJU6677 NJU6677 (1) description for each blocks (1) description for each blocks (1-2)display start line register (1-2)display start line register the display start line register is a pointer register which indicates the address in the display data ram the display start line register is a pointer register which indicates the address in the display data ram corresponding with com corresponding with com 0 0 (normally it display the top line in the lcd panel). this register also operates for (normally it display the top line in the lcd panel). this register also operates for vertical display scroll, the display page change and so on. the display start line set instruction sets the vertical display scroll, the display page change and so on. the display start line set instruction sets the display start address of the display data ram represented in 8-bit to this register. display start address of the display data ram represented in 8-bit to this register. functional description functional description (1-1) busy flag (bf) (1-1) busy flag (bf) while the internal circuits are operating, the busy flag (bf) is "1" and any instruction excepting for the status while the internal circuits are operating, the busy flag (bf) is "1" and any instruction excepting for the status read are inhibited . read are inhibited . the busy flag goes to ?1? from d the busy flag goes to ?1? from d 7 7 terminal when status read instruction is executed. terminal when status read instruction is executed. when enough cycle time over than t when enough cycle time over than t cyc cyc indicated in ? bus timing characteristics? is ensured, no indicated in ? bus timing characteristics? is ensured, no need to check the busy flag for reduction of the mpu loads. need to check the busy flag for reduction of the mpu loads. (1-3) line counter (1-3) line counter the line counter generates the line address of display data ram by the count up operation synchronizing the the line counter generates the line address of display data ram by the count up operation synchronizing the common cycle after the reset operation at the status change of internal fr signal. common cycle after the reset operation at the status change of internal fr signal. (1-4) column address counter (1-4) column address counter the column address counter is 8-bit pre-settable counter addressing the column address of display data ram the column address counter is 8-bit pre-settable counter addressing the column address of display data ram as shown in fig. 1. it is incremented (+1) up to (84) as shown in fig. 1. it is incremented (+1) up to (84) h h by the display data read/write instruction execution. by the display data read/write instruction execution. it stops the count up operation at (84) it stops the count up operation at (84) h h , and it does not count up non existing address area over than (84) , and it does not count up non existing address area over than (84) h h by by the count lock function. this count lock is released by new column address set. the count lock function. this count lock is released by new column address set. the column address counter is independent of the page register. the column address counter is independent of the page register. by the address inverse instruction, the column address decoder inverse the column address of display data by the address inverse instruction, the column address decoder inverse the column address of display data ram corresponding to the segment driver. ram corresponding to the segment driver. (1-5) page register (1-5) page register the page register gives a page address of display data ram as shown in fig. 1. when the mpu accesses the page register gives a page address of display data ram as shown in fig. 1. when the mpu accesses the data with the page change, the page address set instruction is required. the data with the page change, the page address set instruction is required. (1-6) display data ram (1-6) display data ram display data ram is the bit map ram consisting of 15,840 bits to memorize the display data corresponding to display data ram is the bit map ram consisting of 15,840 bits to memorize the display data corresponding to each pixel of lcd panel. the each bit in the display data ram corresponds to the each pixel of the lcd each pixel of lcd panel. the each bit in the display data ram corresponds to the each pixel of the lcd panel and controls the display by following bit data. panel and controls the display by following bit data. when normal display : on="1" , off="0" when normal display : on="1" , off="0" when inverse display : on="0" , off="1" when inverse display : on="0" , off="1" the display data ram outputs 132-bit parallel data in the area addressed by the line counter, and these data the display data ram outputs 132-bit parallel data in the area addressed by the line counter, and these data are set into the display data latch. are set into the display data latch. the access operation from mpu to the display data ram and the data output from the display data ram are the access operation from mpu to the display data ram and the data output from the display data ram are so controlled to operate independently that the data rewriting does not influence with any malfunctions to the so controlled to operate independently that the data rewriting does not influence with any malfunctions to the display.the relation between column address and segment output can inverse by the address inverse instruc- display.the relation between column address and segment output can inverse by the address inverse instruc- tion adc as shown in fig.1. tion adc as shown in fig.1. (1-7) common driver assignment (1-7) common driver assignment the scanning order can be assigned by mask option as shown on table 1. the scanning order can be assigned by mask option as shown on table 1. table 1 table 1 com outputs terminals pad no. 45 88 221 264 pin name c 0 c 43 c 87 c 44 ver.a com 0 com 43 com 87 com 44 ver.b com 87 com 44 com 0 com 43
NJU6677 NJU6677 fig.1 correspondence with display data ram address fig.1 correspondence with display data ram address page address data display pattern line address for example the display start line is 10 h d3,d2,d1,d0 (0,0,0,0) d0 pege 0 00 d1 01 d2 02 d3 03 d4 04 d5 05 d6 06 d7 07 d3,d2,d1,d0 (0,0,0,1) d0 pege 1 08 d1 09 d2 0a d3 0b d4 0c d5 0d d6 0e d7 0f cn out d3,d2,d1,d0 (0,0,1,0) d0 pege 2 10 c0 d1 11 c1 d2 12 c2 d3 13 c3 d4 14 c4 d5 15 c5 d6 16 c6 d7 17 c7 : : : : d0 : : : : 18 c8 d1 19 c9 : : : : : : : : : : : : d6 5e c78 d7 5f c79 d3,d2,d1,d0 (1,1,0,0) d0 pege 12 60 c80 d1 61 c81 d2 62 c82 d3 63 c83 d4 64 c84 d5 65 c85 d6 66 c86 d7 67 c87 d3,d2,d1,d0 (1,1,0,1) d0 pege 13 68 d1 69 d2 6a d3 6b d4 6c d5 6d d6 6e d7 6f d3,d2,d1,d0 (1,1,1,0) d0 pege 14 70 d1 71 d2 72 d3 73 d4 74 d5 75 d6 76 d7 77 | | | | | | | | | | | | | | | | | | | | column addre- ss a d c d 0 ="0" 00 01 02 03 04 05 06 07 08 09 7a 7b 7c 7d 7e 7f 80 81 82 83 d 0 ="1" 83 82 81 80 7f 7e 7d 7c 7b 7a 09 08 07 06 05 04 03 02 01 00 segment output 0 1 2 3 4 5 6 7 8 9 122 123 124 125 126 127 128 129 130 131
NJU6677 NJU6677 (1-8) reset circuit (1-8) reset circuit reset circuit operates the following initializations when the condition of res terminal goes to "l" level. reset circuit operates the following initializations when the condition of res terminal goes to "l" level. initialization initialization 1 1 display off display off 2 2 normal display (non-inverse display) normal display (non-inverse display) 3 3 adc select : normal (adc instruction d adc select : normal (adc instruction d 0 0 =?0?) =?0?) 4 4 read modify write mode off read modify write mode off 5 5 internal power supply (voltage booster) circuits off internal power supply (voltage booster) circuits off 6 6 static drive off static drive off 7 7 driver output off driver output off 8 8 clear the serial interface register clear the serial interface register 9 9 set the address(00) set the address(00) h h to the column address counter to the column address counter 10 10 set the 1st line in the display start line register.page (00) set the 1st line in the display start line register.page (00) h h to the page address register to the page address register 11 11 set the page ?0? to the page address register set the page ?0? to the page address register 12 12 set the evr register to (ff) set the evr register to (ff) h h 13 13 set the all display(1/88 duty) set the all display(1/88 duty) 14 14 set the bias select(1/10 bias) set the bias select(1/10 bias) 15 15 set the 5-time voltage booster set the 5-time voltage booster 16 16 set the n line turn over register (0) set the n line turn over register (0) h h the res terminal should be connected to the reset terminal of mpu for the initialization at the mean time the res terminal should be connected to the reset terminal of mpu for the initialization at the mean time with mpu as shown in "mpu interface example". the period of reset signal requires over than 10us res="l" with mpu as shown in "mpu interface example". the period of reset signal requires over than 10us res="l" level input as shown in "electrical characteristics". after 1us from the rise edge of res signal, the operation level input as shown in "electrical characteristics". after 1us from the rise edge of res signal, the operation goes to normal. goes to normal. when the internal lcd power supply is not used, the external lcd power supply into the NJU6677 must be when the internal lcd power supply is not used, the external lcd power supply into the NJU6677 must be turned on during res = "l". although the condition of res="l" clear each registers and initialize as above, the turned on during res = "l". although the condition of res="l" clear each registers and initialize as above, the oscillation circuit and the output terminal conditions (d oscillation circuit and the output terminal conditions (d 0 0 to d to d 7 7 ) are not influenced. the initialization must be ) are not influenced. the initialization must be performed using res terminal at the power on, to prevent hung up or any incorrect operations. the reset performed using res terminal at the power on, to prevent hung up or any incorrect operations. the reset instruction performs the initialization procedures from no.9 to no.16 as shown in above. instruction performs the initialization procedures from no.9 to no.16 as shown in above. note) the noise into the res terminal should be eliminated to avoid the error on the application with the note) the noise into the res terminal should be eliminated to avoid the error on the application with the careful design. careful design. (1-9) lcd driving (1-9) lcd driving (a) lcd driving circuits (a) lcd driving circuits lcd driving circuits are consisted of 220 multiplexers which operate as 132 segment drivers and 88 common lcd driving circuits are consisted of 220 multiplexers which operate as 132 segment drivers and 88 common drivers. 88 common drivers with the shift register scan the common display signal. the combination of the drivers. 88 common drivers with the shift register scan the common display signal. the combination of the display data, com scan signal and fr signal form into the lcd driving output voltage. the output wave form display data, com scan signal and fr signal form into the lcd driving output voltage. the output wave form is shown in the fig. 7. is shown in the fig. 7. (b) display data latch circuits (b) display data latch circuits display data latch stores 132-bit display data temporarily which is output to lcd driver circuits at a common display data latch stores 132-bit display data temporarily which is output to lcd driver circuits at a common cycle from display data ram addressed by line counter. the instructions of display on/off, display inverse cycle from display data ram addressed by line counter. the instructions of display on/off, display inverse on/off and static drive on/off control only the data in display data latch, therefore, the data in the display on/off and static drive on/off control only the data in display data latch, therefore, the data in the display data ram is not changed. data ram is not changed. (c) line counter and latch signal of latch circuits (c) line counter and latch signal of latch circuits the clock to line counter and latch signal to the latch circuits are generated from the internal display clock the clock to line counter and latch signal to the latch circuits are generated from the internal display clock (cl). the line address of display data ram is renewed synchronizing with display clock(cl). 132 bits display (cl). the line address of display data ram is renewed synchronizing with display clock(cl). 132 bits display data are latched in display latch circuits synchronizing with display clock, and then output to the lcd driving data are latched in display latch circuits synchronizing with display clock, and then output to the lcd driving circuits. the display data transfer to the lcd driving circuits is executed independently with ram access by circuits. the display data transfer to the lcd driving circuits is executed independently with ram access by the mpu. the mpu. (d) display timing generator (d) display timing generator display timing generator generates the timing signal for the display system by combination of the master display timing generator generates the timing signal for the display system by combination of the master clock cl and driving signal fr ( refer to fig.2 ). the frame signal fr and lcd alternative signal generate clock cl and driving signal fr ( refer to fig.2 ). the frame signal fr and lcd alternative signal generate lcd driving waveform of the two frame alternative driving method or n-line inverse driving method. lcd driving waveform of the two frame alternative driving method or n-line inverse driving method.
NJU6677 NJU6677 (e)common timing generation (e)common timing generation the common timing is generated by display clock. the common timing is generated by display clock. -waveform of display timing(without the n-line inverse function, the line inverse register in set to 0) -waveform of display timing(without the n-line inverse function, the line inverse register in set to 0) fig.2 fig.2 -waveform of display timing(with the n-line inverse function, n=7, the line inverse register in set to 6) -waveform of display timing(with the n-line inverse function, n=7, the line inverse register in set to 6) fig.3 fig.3 c l f r c 0 c 1 r a m d a t a s n v d d v 1 v 4 v 5 v d d v 1 v 4 v 5 v d d v 2 v 3 v 5 8 7 8 8 1 2 3 4 5 6 7 8 8 5 8 6 8 7 8 8 1 2 3 4 5 8 7 8 8 1 2 3 4 5 6 7 8 c l f r c 0 c 1 r a m d a t a s n v d d v 1 v 4 v 5 v d d v 1 v 4 v 5 v d d v 2 v 3 v 5 8 5 8 6 8 7 8 8 1 2 3 4 5
NJU6677 NJU6677 t 1 t 2 voltage booster voltage adj. buffer(v/f) ext.pow supply c 1+ ,c 1- to c 4 +,c 4- vr term. l l/h on on on - h l off on on v out open h h off off on v 5 ,v out open open duty 1/8 1/16 1/24 1/32 1/40 1/48 1/56,64 1/72 1/80,88 divide 1/44 1/22 1/15 1/11 1/9 1/7 1/6 1/5 1/4 -the relation between duty and divide -the relation between duty and divide (f) oscillation circuit (f) oscillation circuit the oscillation circuit is a low power cr oscillator incorporating with resistor and capacitor. it generates the oscillation circuit is a low power cr oscillator incorporating with resistor and capacitor. it generates clocks for display timing signal source and voltage booster circuits. the oscillation circuit output frequency is clocks for display timing signal source and voltage booster circuits. the oscillation circuit output frequency is divided as shown in below for display clock cl. divided as shown in below for display clock cl. (g) power supply circuit (g) power supply circuit internal power supply circuit generate the high voltage and bias voltage for the lcd. the power supply internal power supply circuit generate the high voltage and bias voltage for the lcd. the power supply circuit consists of voltage booster (5-time maximum) circuits, regulator circuits, and voltage followers. circuit consists of voltage booster (5-time maximum) circuits, regulator circuits, and voltage followers. the internal power supply is designed for small size lcd panel, therefore it is not suitable for the large size the internal power supply is designed for small size lcd panel, therefore it is not suitable for the large size lcd panel application. if the contrast is not good in the large size lcd panel application, please supply the lcd panel application. if the contrast is not good in the large size lcd panel application, please supply the external. external. the suitable values of the capacitors connecting to the v the suitable values of the capacitors connecting to the v 1 1 to v to v 5 5 terminals and the voltage booster circuit, and terminals and the voltage booster circuit, and the feedback resistors for v the feedback resistors for v 5 5 operational amplifier depend on the lcd panel. and the power consumption with operational amplifier depend on the lcd panel. and the power consumption with the lcd panel is depending on the display pattern. please evaluate with actual lcd module. the lcd panel is depending on the display pattern. please evaluate with actual lcd module. the operation of internal power supply circuits is controlled by the internal power supply on/off instruction. the operation of internal power supply circuits is controlled by the internal power supply on/off instruction. when the internal power supply off instruction is executed, all of the voltage booster circuits, regulator when the internal power supply off instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. in this time, the bias voltage of v circuits, voltage follower circuits are turned off. in this time, the bias voltage of v 1 1 , v , v 2 2 , v , v 3 3 , v , v 4 4 , and v , and v 5 5 for the for the lcd should be supplied from outside, terminals c1 lcd should be supplied from outside, terminals c1 + + , c1 , c1 - - , c2 , c2 + + , c2 , c2 - - , c3 , c3 + + , c3 , c3 - - , c4 , c4 + + , c4 , c4 - - and vr should be open. and vr should be open. the status of internal power supply is selected by t the status of internal power supply is selected by t 1 1 and t and t 2 2 terminal. furthermore the external power supply terminal. furthermore the external power supply operates with some of internal power supply function. operates with some of internal power supply function. when (t when (t 1 1 , t , t 2 2 )=(h, l), c1 )=(h, l), c1 + + , c1 , c1 - - , c2 , c2 + + , c2 , c2 - - ,c3 ,c3 + + , c3 , c3 - - , c4 , c4 + + , c4 , c4 - - terminals for voltage booster circuits are open terminals for voltage booster circuits are open because the voltage booster circuits doesn't operate. therefore lcd driving voltage to the v because the voltage booster circuits doesn't operate. therefore lcd driving voltage to the v out out terminal terminal should be supplied from outside. should be supplied from outside. when (t when (t 1 1 , t , t 2 2 )=(h, h), terminals for voltage booster circuits and vr are open, because the voltage booster )=(h, h), terminals for voltage booster circuits and vr are open, because the voltage booster circuits and voltage adjust circuits do not operate. circuits and voltage adjust circuits do not operate.
NJU6677 NJU6677 : these switches should be open during the power save mode. : these switches should be open during the power save mode. v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s t 1 t 2 power supply applications power supply applications (1)external power supply operation. (1)external power supply operation. (2)internal power supply operation. (2)internal power supply operation. (voltage booster, voltage adj., buffer(v/f)) (voltage booster, voltage adj., buffer(v/f)) internal power supply on (instruction) (t internal power supply on (instruction) (t 1, 1, t t 2 2 )=(l,l) )=(l,l) + + + + + + v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s t 1 t 2 c 1 + + + + + v d d v r v 5 c 4 + c 3 + c 2 - c 2 + c 1 - c 4 - c 3 - (4)external power supply operation adjusted (4)external power supply operation adjusted voltage to v5. voltage to v5. internal power supply (instruction) (t internal power supply (instruction) (t 1 1 ,t ,t 2 2 ) =(h,h) ) =(h,h) (3)external power supply operation with (3)external power supply operation with voltage adjustment,3 buffer(v/f) voltage adjustment,3 buffer(v/f) internal power supply on (instruction) (t internal power supply on (instruction) (t 1 1 ,t ,t 2 2 ) = (h,l) ) = (h,l) + + + + v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s + t 1 t 2 v d d v r v 5 + + + + v d d v 1 v 2 v 3 v 4 v 5 v o u t v s s t 1 t 2
NJU6677 NJU6677 the NJU6677 distinguishes the signal on the data bus by combination of a0, rd and wr. the decode of the the NJU6677 distinguishes the signal on the data bus by combination of a0, rd and wr. the decode of the instruction and execution performs depending on the internal timing only neither the external clock. in case of instruction and execution performs depending on the internal timing only neither the external clock. in case of serial interface, the data input as msb first serially. serial interface, the data input as msb first serially. the table. 4 shows the instruction codes of the NJU6677. the table. 4 shows the instruction codes of the NJU6677. instruction code description a0 rd w- r d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (1) display on/off 0 1 0 1 0 1 0 1 1 1 0 1 lcd display on/off 0:off 1:on (2) display start line set high order 4bits 0 1 0 0 1 0 1 high order address determine the display line of ram to the com0. (set the higher order 4bits) display start line set lower order 4bits 0 1 0 0 1 1 0 lower order address determine the display line of ram to the com0. (set the lower order 4bits) (3) page address set 4bits 0 1 0 1 1 0 0 page address set the 4 bit page of dd ram to the page address register (4) column address set high order 4bits 0 1 0 0 0 0 1 high order column add . set the higher order 4 bits column address to the reg. column address set lower order 4bits 0 1 0 0 0 0 0 lower order column add. set the lower order 4 bits column address to the reg. (5) status read 0 0 1 status 0 0 0 0 read out the internal status (6) write display data 1 1 0 write data write the data into the display data ram (7) read display data 1 0 1 read data read the data from the display data ram (8) normal or inverse of on/off set 0 1 0 1 0 1 0 0 1 1 0 1 inverse the on and off display 0:normal 1:inverse (9) whole display on /normal display 0 1 0 1 0 1 0 0 1 0 0 1 whole display turns on 0:normal 1:whole disp. on (10) sub instruction table mode 0 1 0 0 1 1 1 0 0 0 0 set the sub instruction table. (11) partial display 1st block, set start display unit 0 1 0 0 0 0 0 start display unit set the start display unit of 1st block. 1st block, set the number of display units 0 1 0 0 0 0 1 number of display units set the number of display units of 1st block. 2nd block, set start display unit 0 1 0 0 0 1 0 start display unit set the start display unit of 2nd block. 2nd block, set the number of display units 0 1 0 0 0 1 1 number of display units set the number of display units of 2nd block. partial display on 0 1 0 0 1 0 0 0 0 0 0 it comes off the mode to set and a display is executed. (12) n-line inverse drive set register set higher order 2 bits 0 1 0 0 1 0 1 * * higher order set the number of inverse drive line. register set lower order 4 bits 0 1 0 0 1 1 0 lower order set the number of inverse drive line. n-line inverse drive set is executed. 0 1 0 0 1 1 1 0 0 0 0 the execution of the line inverse drive. (13) evr register set evr register set higher order 4 bits 0 1 0 1 0 0 0 evr data higher order set the v 5 output level to the evr register. (higher order 4 bits) evr register set lower order 4 bits 0 1 0 1 0 0 1 evr data lower order set the v 5 output level to the evr register. (lower order 4 bits) evr register set is executed. 0 1 0 1 0 1 0 0 0 0 0 the execution of the evr. (14) end of sub instruction table mode 0 1 0 0 1 1 1 0 0 0 1 it ends the setting of sub instruction table. (*:don't care) (*:don't care) (2) instruction (2) instruction table 4. instruction code table 4. instruction code
NJU6677 NJU6677 instruction code description a0 rd wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 (15) bias select 0 1 0 1 0 1 1 * bias select the bias (7 patterns) (16) voltage booster circuits multiple select 0 1 0 0 0 1 1 0 0 boost multiple set the booster circuits (2 to 5 times) (17) read modify write /end 0 1 0 1 1 1 0 0 0 0 0 1 read modify write mode d 0 =0:on d 0 =1:end (18) reset 0 1 0 1 1 1 0 0 0 1 0 initialize the internal circuits (19) internal power supply on/off 0 1 0 0 0 1 0 0 0 0 0 1 0:int. power supply off 1:int. power supply on (20) lcd driving voltage set 0 1 0 0 0 1 0 0 0 1 0 1 set lcd driving voltage after the internal (external) power supply is turned on (21) power save (dual command) set the power save mode (lcd display off +whole display turns on) (22) adc select 0 1 0 1 0 1 0 0 0 0 0 1 set the dd ram vs segment d 0 =0:normal d 0 =1:inverse (*:don't care) (*:don't care)
NJU6677 NJU6677 (3-1) display on/off (3-1) display on/off a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 1 1 d this instruction executes whole display on/off without relationship of the data in the display data ram and this instruction executes whole display on/off without relationship of the data in the display data ram and internal conditions. internal conditions. (3) explanation of instruction code (3) explanation of instruction code d 0:display off d 0:display off 1:display on 1:display on (3-2) display start line (3-2) display start line this instruction sets the line address of display data ram corresponding the com0 terminal (the highest this instruction sets the line address of display data ram corresponding the com0 terminal (the highest position line of display in normal application). the display area is fixed automatically by number of display line position line of display in normal application). the display area is fixed automatically by number of display line which corresponds the display duty ratio from the pointed line address as the start line. this instruction realizes which corresponds the display duty ratio from the pointed line address as the start line. this instruction realizes the vertical smooth scroll with extra display ram or the page address change by dynamic line addressing. in the vertical smooth scroll with extra display ram or the page address change by dynamic line addressing. in this time, the contents of ram are not changed. this time, the contents of ram are not changed. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 line address(hex) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 0 1 1 1 0 1 1 1 77 (3-3) page address set (3-3) page address set when mpu accesses the display data ram, the page address must be selected before the data writing. the when mpu accesses the display data ram, the page address must be selected before the data writing. the access to the display data ram is available by the page and column address set (refer the fig. 1). the page access to the display data ram is available by the page and column address set (refer the fig. 1). the page address change does not influence with the display. address change does not influence with the display. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 0 0 a 3 a 2 a 1 a 0 a 3 a 2 a 1 a 0 page 0 0 0 0 0 0 0 0 1 1 : : : : 1 1 1 0 14 a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 a 7 a 6 a 5 a 4 0 1 0 0 1 1 0 a 3 a 2 a 1 a 0 (*:don't care) (*:don't care)
NJU6677 NJU6677 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address(hex) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 0 0 0 0 0 1 1 83 (3-4) column address (3-4) column address a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 a 7 a 6 a 5 a 4 when mpu accesses the display data ram, the page address (refer(3-3) ) and column address set are when mpu accesses the display data ram, the page address (refer(3-3) ) and column address set are required before the data writing. the column address set requires twice address set which are higher order 4 required before the data writing. the column address set requires twice address set which are higher order 4 bits address set and lower order 4 bits. when the mpu accesses the display data ram sequentially, the bits address set and lower order 4 bits. when the mpu accesses the display data ram sequentially, the column address is increase one by one automatically, therefore, the mpu can access only the data sequen- column address is increase one by one automatically, therefore, the mpu can access only the data sequen- tially without address set. tially without address set. after writing 1page data, page address setting is required due to page address doesn't increase automatically. after writing 1page data, page address setting is required due to page address doesn't increase automatically. the increment of the column address is stopped at the address of (83) the increment of the column address is stopped at the address of (83) h h automatically, and the page address is automatically, and the page address is not changed even if the column address increase to (83) not changed even if the column address increase to (83) h h and stop. in this time the page address is not and stop. in this time the page address is not changed. changed. 0 1 0 0 0 0 0 a 3 a 2 a 1 a 0 higher order higher order lower order lower order (3-5) status read (3-5) status read this instruction reads out the internal status of "busy", ?adc", "on/off" and "reset". this instruction reads out the internal status of "busy", ?adc", "on/off" and "reset". a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 busy adc on/off reset 0 0 0 0 busy busy : busy=1 indicate the operating or the reset cycle. : busy=1 indicate the operating or the reset cycle. the instruction can be input after the busy status change to "0". the instruction can be input after the busy status change to "0". adc adc : indicate the output correspondence of column (segment) address and segment driver. : indicate the output correspondence of column (segment) address and segment driver. 0 :counterclockwise output (inverse) column address 131-n <---> segment driver n 0 :counterclockwise output (inverse) column address 131-n <---> segment driver n 1 :clockwise output (normal) column address n <---> segment driver n 1 :clockwise output (normal) column address n <---> segment driver n (note) the data "0=inverse" and "1=normal" of adc is inverted with the adc select (note) the data "0=inverse" and "1=normal" of adc is inverted with the adc select instruction of "1=inverse" and "0=normal". instruction of "1=inverse" and "0=normal". on/off : indicate the whole display on/off status. on/off : indicate the whole display on/off status. 0 : whole display "on 0 : whole display "on 1 : whole display "off" 1 : whole display "off" (note) the data "0=on" and "1=off" of display on/off status read out is inverted with the (note) the data "0=on" and "1=off" of display on/off status read out is inverted with the display on/off instruction data of "1=on" and "0=off". display on/off instruction data of "1=on" and "0=off". reset : indicate the initializing by res signal or reset instruction. reset : indicate the initializing by res signal or reset instruction. 0 : - 0 : - 1 : initialization period 1 : initialization period
NJU6677 NJU6677 (3-6) write display data (3-6) write display data a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data this instruction writes the 8-bit data on the data bus into the display data ram. the column address in- this instruction writes the 8-bit data on the data bus into the display data ram. the column address in- creases "1" automatically after data writing, therefore, the mpu can write the 8-bit data into the display data creases "1" automatically after data writing, therefore, the mpu can write the 8-bit data into the display data ram continuously without any address setting after the start address setting. ram continuously without any address setting after the start address setting. (3-7) read display data (3-7) read display data a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data this instruction reads out the 8-bit data from display data ram addressed by the column and page address. this instruction reads out the 8-bit data from display data ram addressed by the column and page address. the column address increase "1" automatically after data reading out, therefore, the mpu can read out the 8- the column address increase "1" automatically after data reading out, therefore, the mpu can read out the 8- bit data from the display data ram without any address setting after the start address setting. one time of bit data from the display data ram without any address setting after the start address setting. one time of dummy read must operate after column address set as the explanation in "(5-4) access to the display data dummy read must operate after column address set as the explanation in "(5-4) access to the display data ram and internal register". in the serial interface mode, the display data is not read out. ram and internal register". in the serial interface mode, the display data is not read out. (3-8) normal or inverse on/off set (3-8) normal or inverse on/off set a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 1 d this instruction changes the condition of display turn on and off as normal or inverse. the contents of display this instruction changes the condition of display turn on and off as normal or inverse. the contents of display data ram is not changed by this instruction execution. data ram is not changed by this instruction execution. d 0 : normal d 0 : normal ram data "1" correspond to "on" ram data "1" correspond to "on" 1 : inverse 1 : inverse ram data "0" correspond to "on" ram data "0" correspond to "on" (3-9) whole display on (3-9) whole display on d 0 : normal display d 0 : normal display 1 : whole display turn on 1 : whole display turn on a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 0 d when whole display on instruction is executed in the display off status, the internal circuits go when whole display on instruction is executed in the display off status, the internal circuits go to the power save mode (refer to the (s) power save). to the power save mode (refer to the (s) power save). this instruction turns on the all pixels indipendent of the contents of display data ram. in this time, the this instruction turns on the all pixels indipendent of the contents of display data ram. in this time, the contents of display data ram is not changed and kept. this instruction takes precedence over the "normal or contents of display data ram is not changed and kept. this instruction takes precedence over the "normal or inverse on/off set instruction". inverse on/off set instruction".
NJU6677 NJU6677 (3-10) sub instruction table mode (3-10) sub instruction table mode this instruction switches the instruction table from the main to the sub. the sub instruction table contains this instruction switches the instruction table from the main to the sub. the sub instruction table contains instructions of partial display, n-line inverse drive set and evr register set as mentioned in (11), (12) and (13). instructions of partial display, n-line inverse drive set and evr register set as mentioned in (11), (12) and (13). the instruction of sub instruction table mode must be executed before above 3 sub instructions execution. the the instruction of sub instruction table mode must be executed before above 3 sub instructions execution. the instruction of end of sub instruction table mode (14) switches the instruction table from the sub to the main. if instruction of end of sub instruction table mode (14) switches the instruction table from the sub to the main. if any main instructions are written in the sub instruction mode, the NJU6677 will malfunction. any main instructions are written in the sub instruction mode, the NJU6677 will malfunction. sub instruction table mode set sub instructions. end of sub instruction table mode. -set sub instruction table flow is shown below: -set sub instruction table flow is shown below: switches to sub instruction table mode. switches to sub instruction table mode. switches to main instruction mode. switches to main instruction mode. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0
NJU6677 NJU6677 u n i t 1 u n i t 4 u n i t 2 u n i t 5 u n i t 3 u n i t 6 u n i t 8 u n i t 7 u n i t 9 u n i t 1 0 u n i t 0 ( 8 c o m m o n s ) ( 8 c o m m o n s ) the partial display operates by the conbination of instructions which area unit number of start position start unit the partial display operates by the conbination of instructions which area unit number of start position start unit block in the display area and a number of display unit from start position to end as a block. the number of block in the display area and a number of display unit from start position to end as a block. the number of block is set up to two. block is set up to two. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 d d d d partial display instruction partial display instruction 0 1 0 0 0 0 1 d d d d 0 1 0 0 0 1 0 d d d d start display start display unit unit the number of the number of display units display units start display start display unit unit the number of the number of display units display units 0 1 0 0 0 1 1 d d d d d :unit number (hex.) d :unit number (hex.) incase of full display (1/88 duty), all of units on the display are selected when the first incase of full display (1/88 duty), all of units on the display are selected when the first start unit is set to ?0? (0,0,0,0) and the second number of display unit is set to ?11? start unit is set to ?0? (0,0,0,0) and the second number of display unit is set to ?11? (1,0,1,1). in this time, the second block settings are ignored. (1,0,1,1). in this time, the second block settings are ignored. in case of only one block display, the second block settings are ignored when the in case of only one block display, the second block settings are ignored when the second start unit is set to ?0? (0,0,0,0) and the second display unit number is set to ?0? second start unit is set to ?0? (0,0,0,0) and the second display unit number is set to ?0? (0,0,0,0). (0,0,0,0). keep the order of partial display instruction sequence. keep the order of partial display instruction sequence. do not set over ?unit 10? the display data in dd ram are assigned continuously from do not set over ?unit 10? the display data in dd ram are assigned continuously from page 0 for all of display block, even if non-display area is existed between the first page 0 for all of display block, even if non-display area is existed between the first block and the second. block and the second. 1 1 st st block block 2 2 nd nd block block partial display partial display on on 0 1 0 0 1 0 0 0 0 0 0 (3-11) partial display (3-11) partial display this instruction divides the active display area in a lcd panel to 11 units consisting of 8 commons per unit this instruction divides the active display area in a lcd panel to 11 units consisting of 8 commons per unit and displays one or two blocks of active display area consisting of a unit or more. in the partial display mode, and displays one or two blocks of active display area consisting of a unit or more. in the partial display mode, the display duty ratio is set automatically according to the number of unit in a block or two. the display duty ratio is set automatically according to the number of unit in a block or two. therefore, the partial display function realizes to go down the lcd driving voltage according to the display therefore, the partial display function realizes to go down the lcd driving voltage according to the display duty ratio. as a result, the operation current of display system is much saved against the full display mode. duty ratio. as a result, the operation current of display system is much saved against the full display mode. the display units the display units 88-common 88-common 132-segment 132-segment note) note) after execution of the next instruction, the display mode is changed to the after execution of the next instruction, the display mode is changed to the partial display and the duty is changed automatically. partial display and the duty is changed automatically.
NJU6677 NJU6677 the example of partial display setting the example of partial display setting active display-block active display-block the above partial display condition is set as follows: the above partial display condition is set as follows: 1)set sub instruction mode 1)set sub instruction mode 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 1 a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 3)end sub instruction mode 3)end sub instruction mode although the partial display instruction changes duty cycle ratio automatically and display area, lcd driving although the partial display instruction changes duty cycle ratio automatically and display area, lcd driving voltage, bias and others are not changed. therefore, the instruction of lcd driving voltage ?off? (d=0) must voltage, bias and others are not changed. therefore, the instruction of lcd driving voltage ?off? (d=0) must be set before partial display operation, and the other instructions such as the n-line inverse drive set, evr be set before partial display operation, and the other instructions such as the n-line inverse drive set, evr register set, bias select and voltage booster select should be set for optimum display-contrast. the ?end of sub register set, bias select and voltage booster select should be set for optimum display-contrast. the ?end of sub instruction mode? is required before these instructions in order to prevent momentary flickering. instruction mode? is required before these instructions in order to prevent momentary flickering. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 set sub instruction set sub instruction mode. mode. 2)set partial display conditions 2)set partial display conditions a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 1 end sub instruction end sub instruction mode. back to main mode. back to main instruction mode. instruction mode. unit 2 unit 2 unit 3 unit 3 unit 9 unit 9 unit 10 unit 10 unit 0 unit 0 unit 1 unit 1 unit 4 unit 4 unit 8 unit 8 unit 7 unit 7 unit 5 unit 5 unit 6 unit 6 1 1 st st block block 2 2 nd nd block block 1 1 st st block, block, set start set start display unit to ?0? display unit to ?0? 1 1 st st block, block, set the number set the number of display units to ?2? of display units to ?2? 2 2 nd nd block, block, set start set start display unit to ?4? display unit to ?4? 2 2 nd nd block, block, set the number set the number of display units to ?5? of display units to ?5? partial display on. partial display on. in this case, 1/56 duty. (duty=1/(number of display units x 8)) in this case, 1/56 duty. (duty=1/(number of display units x 8))
NJU6677 NJU6677 internal power supply off sub instruction table mode partial display n-line inverse drive set evr register set end sub instruction table mode bias select voltage booster times select wait time internal power supply on -set partial display flow is shown below: -set partial display flow is shown below: this instruction sets a line number for inversion of lcd driving signal levels between ?1? and ?0?. it reduces this instruction sets a line number for inversion of lcd driving signal levels between ?1? and ?0?. it reduces the stripe shadow(crosstalk) and stabilizes display quality. the n- the stripe shadow(crosstalk) and stabilizes display quality. the n- line inverse number is set according to the line inverse number is set according to the result of actual lcd panel display. result of actual lcd panel display. the instructions must be input in order of followings. the instructions must be input in order of followings. these instructions are sub instruction sets and must be these instructions are sub instruction sets and must be set after (3-10)sub instruction table mode. set after (3-10)sub instruction table mode. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 * * a 5 a 4 0 1 0 0 1 1 0 a 3 a 2 a 1 a 0 higher order higher order low order low order a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 the actual operation starts after following instruction. the actual operation starts after following instruction. (3-12) n-line inverse drive mode (3-12) n-line inverse drive mode (*:don't care) (*:don't care) a 5 a 4 a 3 a 2 a 1 a 0 inverse line 0 0 0 0 0 0 - 0 0 0 0 0 1 2 : : : : 1 1 1 1 1 1 64
NJU6677 NJU6677 this instruction controls voltage adjustment circuits of internal lcd power supply and changes lcd driving this instruction controls voltage adjustment circuits of internal lcd power supply and changes lcd driving voltage ?v5?. finally, it adjusts the contrast of lcd display. by setting a data into evr register, v5 output voltage ?v5?. finally, it adjusts the contrast of lcd display. by setting a data into evr register, v5 output voltage selects one condition out of 201-voltage conditions. the range of v voltage selects one condition out of 201-voltage conditions. the range of v 5 5 voltage is adjusted by setting voltage is adjusted by setting external resistors as mentioned in "(4)(b) voltage adjust circuits". external resistors as mentioned in "(4)(b) voltage adjust circuits". this instruction is sub instruction and it must be set after (3-10) sub instruction table mode. this instruction is sub instruction and it must be set after (3-10) sub instruction table mode. a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v lcd 0 0 1 1 0 1 1 1 low : : : : 1 1 1 1 1 1 1 1 high v v lcd lcd =v =v dd dd -v -v 5 5 when evr doesn't use, set the evr register to (1,1,1,1,1,1,1,1). when evr doesn't use, set the evr register to (1,1,1,1,1,1,1,1). a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 0 a 7 a 6 a 5 a 4 0 1 0 1 0 0 1 a 3 a 2 a 1 a 0 a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 0 the actual operation starts after following instruction. the actual operation starts after following instruction. (3-13) evr register set (3-13) evr register set (3-14) end of sub instruction table mode (3-14) end of sub instruction table mode "end of sub instruction table mode" instruction switches instruction table from sub to main. "end of sub instruction table mode" instruction switches instruction table from sub to main. (11)partial display, (12)n-line inverse drive mode, and (13)evr are sub instruction sets on the sub instruction (11)partial display, (12)n-line inverse drive mode, and (13)evr are sub instruction sets on the sub instruction table. the instruction of ?end of sub instruction mode? must be set after these sub instruction sets. the table. the instruction of ?end of sub instruction mode? must be set after these sub instruction sets. the NJU6677 may occur in-correct operation if any main instructions on the main instruction table are input in NJU6677 may occur in-correct operation if any main instructions on the main instruction table are input in mode of sub instruction table. mode of sub instruction table. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 1
NJU6677 NJU6677 (3-15) bias select (3-15) bias select a 2 a 1 a 0 bias 0 0 0 1/4 0 0 1 1/5 0 1 0 1/6 0 1 1 1/7 1 0 0 1/8 1 0 1 1/9 1 1 * 1/10 this instruction decides the value of lcd driving voltage bias ratio. this instruction decides the value of lcd driving voltage bias ratio. especially, the bias should be selected for display quality in partial mode. especially, the bias should be selected for display quality in partial mode. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 1 * a 2 a 1 a 0 (3-16) voltage booster circuit multiple select (3-16) voltage booster circuit multiple select a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 a 1 a 0 this instruction selects a voltage boost time. this instruction selects a voltage boost time. the multiple must be selected the voltage boost times according to the maximum boost times by the external the multiple must be selected the voltage boost times according to the maximum boost times by the external capacitors connections or less. especially, the multiple should be selected for display quality and saving capacitors connections or less. especially, the multiple should be selected for display quality and saving operation current in partial display mode. operation current in partial display mode. (*:don't care) (*:don't care) command booster multiple a 1 a 0 5times external capacitors connections 4times external capacitors connections 3times external capacitors connections 2times external capacitors connections 0 0 2-time 0 1 3-time 2-time 1 0 4-time 3-time 2-time 1 1 5-time 4-time 3-time 2-time
NJU6677 NJU6677 (3-17) read modify write/end (3-17) read modify write/end this instruction sets the read modify write mode for the column address increment control. in mode of the this instruction sets the read modify write mode for the column address increment control. in mode of the read modify write, the column address increases "1" automatically when the display data write instruction is read modify write, the column address increases "1" automatically when the display data write instruction is executed, but the address does not change when the display data read instruction is executed. this status is executed, but the address does not change when the display data read instruction is executed. this status is continued until end instruction execution. when the end instruction (d=1) is input, the column address goes continued until end instruction execution. when the end instruction (d=1) is input, the column address goes back to the start address before the read modify write instruction input. this function reduces the load of back to the start address before the read modify write instruction input. this function reduces the load of mpu for repeating the display data change in the fixed area (ex. cursor blink). mpu for repeating the display data change in the fixed area (ex. cursor blink). d=?1? to release the read modify write mode and the column address back to the address where the read d=?1? to release the read modify write mode and the column address back to the address where the read modify write mode setting. modify write mode setting. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 0 d note) in mode of the read modify write, any instructions except for column address set can note) in mode of the read modify write, any instructions except for column address set can execute. execute. - sequence of cursor blink display - sequence of cursor blink display d 0 : read modify write on d 0 : read modify write on 1 : end 1 : end page address set set to the start address of cursor display column address set read modify write start the read modify write dummy read read the data as dummy data read data inverse by mpu data write dummy read data read data write end end the read modify write no finish? yes
nju667 nju667 7 7 (3-18) reset (3-18) reset this instruction executes the following initialization. this instruction executes the following initialization. initialization initialization (1) set the address (00) (1) set the address (00) h h into the column address counter. into the column address counter. (2) set the address (00) (2) set the address (00) h h into the display start line register. into the display start line register. (3) set the page "0" into the page address register. (3) set the page "0" into the page address register. (4) set 0 to the evr register to (ff) (4) set 0 to the evr register to (ff) h h . . (5) set the all display(1/88 duty) (5) set the all display(1/88 duty) (6) set the bias select(1/10 bias) (6) set the bias select(1/10 bias) (7) set the 5-time voltage booster. (7) set the 5-time voltage booster. (8) set the n-line inverse register (0) (8) set the n-line inverse register (0) h h in this time, the display data ram is not influenced. in this time, the display data ram is not influenced. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 1 0 the reset signal input to the res terminal (hardware reset) must be input for the power on initialization. reset the reset signal input to the res terminal (hardware reset) must be input for the power on initialization. reset instruction does not perform completely in stead of hardware reset using the res terminal. instruction does not perform completely in stead of hardware reset using the res terminal. (3-19) internal power supply on/off (3-19) internal power supply on/off this instruction set the condition of internal power supply on/off. this instruction set the condition of internal power supply on/off. voltage booster voltage booster circuits, voltage regulator circuits, voltage regulator and voltage follower operate at on. to operate the and voltage follower operate at on. to operate the voltage booster voltage booster circuits, the oscillation circuits must be circuits, the oscillation circuits must be operating. operating. d 0 : internal power supply off d 0 : internal power supply off 1 : internal power supply on 1 : internal power supply on a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 0 0 d the internal power supply must be off when external power supply using. the internal power supply must be off when external power supply using. *1 the set up period of internal power supply on depends on the *1 the set up period of internal power supply on depends on the step up step up capacitors, voltage stabilizer capacitors, voltage stabilizer capacitors, vdd and vlcd. capacitors, vdd and vlcd. therefore it requires the actual evaluation using the lcd module to get the correct time. (refer to the therefore it requires the actual evaluation using the lcd module to get the correct time. (refer to the (4)(d) fig.4) (4)(d) fig.4)
nju667 nju667 7 7 0 0.2 0.4 0.6 0.8 1 1.2 0 20 40 60 80 100 c3 to c7[uf] time[ms] cout=1 to 4.7[uf] the wait time [typical performance] vdd=2.7v,vlcd=7v,ta=25c (3-20) lcd driving voltage set (3-20) lcd driving voltage set this instruction controls lcd driving waveform output through the com/seg terminals. this instruction controls lcd driving waveform output through the com/seg terminals. a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 0 1 d the NJU6677 contains low power lcd driving voltage generator circuit reducing own operation current. the NJU6677 contains low power lcd driving voltage generator circuit reducing own operation current. therefore, it requires the following sequence procedures at power on for the power source stabilized operation. therefore, it requires the following sequence procedures at power on for the power source stabilized operation. - lcd driving power supply on/off sequences - lcd driving power supply on/off sequences the following sequences are required when the power supply is turned on/off. the following sequences are required when the power supply is turned on/off. when the power supply is turned on again after the turn off (by the power save instruction), the power save when the power supply is turned on again after the turn off (by the power save instruction), the power save release sequence ((3-21) power save) is required. release sequence ((3-21) power save) is required. *1 the wait time depends on the c *1 the wait time depends on the c 1 1 to c to c 9 9 , c , c out out capacitors (refer (4) (d)fig.4), v capacitors (refer (4) (d)fig.4), v dd dd and v and v lcd lcd voltage. voltage. therefore it requires the actual evaluation using the lcd module to get the correct time. (refer to the therefore it requires the actual evaluation using the lcd module to get the correct time. (refer to the following graph.) following graph.) t.b.d. t.b.d. d 0 : lcd driving waveform output off d 0 : lcd driving waveform output off 1 : lcd driving waveform output on 1 : lcd driving waveform output on turn on sequence turn on sequence output assign. register set evr register set internal power supply on or external power supply on (wait time) *1 lcd driving voltage set to on display off whole display on internal power supply off or external power supply off lcd driving voltage set to off turn off sequence turn off sequence
nju667 nju667 7 7 (3-21) power save(dual command) (3-21) power save(dual command) when both of display off and whole display on are executed, the internal circuits go to the power save mode when both of display off and whole display on are executed, the internal circuits go to the power save mode and the operating current is reduced as some as the stand by current. and the operating current is reduced as some as the stand by current. the internal status in the power save mode is shown in follows; the internal status in the power save mode is shown in follows; (1) stop the oscillation circuits and internal power supply circuits operation. (1) stop the oscillation circuits and internal power supply circuits operation. (2) stop the lcd driving. segment and common drivers output v (2) stop the lcd driving. segment and common drivers output v dd dd level. level. (3) keep the display data and operating mode just before the power save mode. (3) keep the display data and operating mode just before the power save mode. (4) all of lcd driving bias voltage fix to the v (4) all of lcd driving bias voltage fix to the v dd dd level. level. the power save and its release perform according to the following sequences. the power save and its release perform according to the following sequences. display off whole display on lcd driving voltage set to off normal display display on (wait time) lcd driving voltage set to on *1 in the power save sequence, the power save mode is started after the second instruction "whole display *1 in the power save sequence, the power save mode is started after the second instruction "whole display on". on". *2 in the power save release sequence, the power save mode is released after the normal display instruction *2 in the power save release sequence, the power save mode is released after the normal display instruction (whole display off). (whole display off). the instruction of display on is input at any timing after the instruction of normal display in power save the instruction of display on is input at any timing after the instruction of normal display in power save release sequence. release sequence. *3 until "lcd driving voltage set to on" execution, NJU6677 operating current is higher than usual state and *3 until "lcd driving voltage set to on" execution, NJU6677 operating current is higher than usual state and all com/seg terminals output v all com/seg terminals output v dd dd level continuously. level continuously. *4 in case of the external power supply for lcd driving, it should be turned off and made condition like as *4 in case of the external power supply for lcd driving, it should be turned off and made condition like as unconnection or connected to v unconnection or connected to v dd dd before the power save mode or at the same time. in this time, v before the power save mode or at the same time. in this time, v out out terminal should be made condition like as disconnection or connected to the lowest voltage of the system terminal should be made condition like as disconnection or connected to the lowest voltage of the system (v (v 5 5 level from the external power supply). level from the external power supply). power save release sequence power save release sequence power save sequence power save sequence (whole display off) (whole display off) (3-22) adc select (3-22) adc select a0 rd r/w wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 d d 0 : clockwise output (normal) d 0 : clockwise output (normal) 1 : counterclockwise output (inverse) 1 : counterclockwise output (inverse) this instruction set the correspondence of column address in the display data ram and segment driver this instruction set the correspondence of column address in the display data ram and segment driver output. (see fig. 1.) by this instruction, the order of segment output can be changed by the software, and no output. (see fig. 1.) by this instruction, the order of segment output can be changed by the software, and no restriction of the lsi placement against the lcd panel. restriction of the lsi placement against the lcd panel.
nju667 nju667 7 7 (a) 5-time voltage booster circuits (a) 5-time voltage booster circuits 5-time voltage booster circuits connecting five capacitors between c1 5-time voltage booster circuits connecting five capacitors between c1 + + and c1 and c1 - - , c2 , c2 + + and c2 and c2 - - , c3 , c3 + + and c3 and c3 - - , c4 , c4 + + and c4 and c4 - - , v , v ss ss and v and v out out boost the voltage of v boost the voltage of v dd dd - v - v ss ss to negative voltage (v to negative voltage (v dd dd common) and output the common) and output the boosted voltage from the v boosted voltage from the v out out terminal. it selects one of boost time from 2 to 5 times by external capacitors terminal. it selects one of boost time from 2 to 5 times by external capacitors connection. furthermore, it also selects one of boost time by ?voltage booster circuits multiple select? instruc- connection. furthermore, it also selects one of boost time by ?voltage booster circuits multiple select? instruc- tion. the boost voltage and the voltage booster circuits are shown in below. voltage booster circuits requires tion. the boost voltage and the voltage booster circuits are shown in below. voltage booster circuits requires the clock signals from internal oscillation circuit, therefore, the oscillation circuits must be operating when the clock signals from internal oscillation circuit, therefore, the oscillation circuits must be operating when voltage boost operation. the boost voltage times are shown in below. when 5-time voltage boost operation, voltage boost operation. the boost voltage times are shown in below. when 5-time voltage boost operation, the operation voltage of v the operation voltage of v dd dd -v -v out out should be less than 18v. should be less than 18v. (4) internal power supply (4) internal power supply v v dd dd =+3v =+3v v v ss ss = = + + 0v 0v v v out out =-v =-v dd dd =-3v =-3v v v out out =-2v =-2v dd dd =-6v =-6v v v out out =-3v =-3v dd dd =-9v =-9v v v out out =-4v =-4v dd dd =-12v =-12v 2-time voltage 3-time voltage 4-time voltage 5-time voltage 2-time voltage 3-time voltage 4-time voltage 5-time voltage examples for connecting the capacitors examples for connecting the capacitors v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + + + + + v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + + + + 5-time voltage 4-time voltage 5-time voltage 4-time voltage 3-time voltage 2-time voltage 3-time voltage 2-time voltage v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + + + v s s c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - v o u t + +
nju667 nju667 7 7 (b)voltage adjust circuits (b)voltage adjust circuits the boosted voltage of v the boosted voltage of v out out output from v output from v 5 5 through the voltage adjust circuits for lcd driving. the output through the voltage adjust circuits for lcd driving. the output voltage of v voltage of v 5 5 is adjusted by changing the ra and rb within the range of | v is adjusted by changing the ra and rb within the range of | v 5 5 | < | v | < | v out out |. the output voltage |. the output voltage is is calculated by the following formula. calculated by the following formula. v v lcd lcd = v = v dd dd -v -v 5 5 = (1+rb/ra)v = (1+rb/ra)v reg (1) reg (1) fig. 3 fig. 3 v d d v 5 v r e g r 1 r 2 r 3 r b r a v r the voltage of v the voltage of v reg reg is a standard voltage produced from built-in bleeder resistance. v is a standard voltage produced from built-in bleeder resistance. v reg reg is possible to be is possible to be fine-adjusted by evr functions mentioned in (c). fine-adjusted by evr functions mentioned in (c). for fine-adjustment of v5, r2 as variable resistor, r1 and r3 as fixed constant should be connected to v for fine-adjustment of v5, r2 as variable resistor, r1 and r3 as fixed constant should be connected to v dd dd terminal, vr and v terminal, vr and v 5, 5, as shown in fig.3. as shown in fig.3. [ design example for r1, r2 and r3 / reference ] [ design example for r1, r2 and r3 / reference ] - r1+r2+r3=5m - r1+r2+r3=5m w w (determined by the current flown between v (determined by the current flown between v dd dd -v -v 5 5 ) ) - variable voltage range by the r2. -6v to -7.5v (v - variable voltage range by the r2. -6v to -7.5v (v lcd lcd =v =v dd dd -v -v 5 5 --> 9.0v to 10.5v) --> 9.0v to 10.5v) (determined by the lcd electrical characteristics) (determined by the lcd electrical characteristics) - v - v reg reg =3v(in case of evr=(ff) =3v(in case of evr=(ff) h h ) ) - r1, r2 and r3 are calculated by above conditions and the formula of (1) to below; - r1, r2 and r3 are calculated by above conditions and the formula of (1) to below; r1=2.0m r1=2.0m w w , r2=0.5m , r2=0.5m w w , r3=2.5m , r3=2.5m w w * if the power supply voltage between v * if the power supply voltage between v dd dd and v and v ss ss changes, v changes, v 5 5 changes too. therefore the power supply changes too. therefore the power supply voltage should be stabilized for v voltage should be stabilized for v 5 5 stable operation. stable operation.
nju667 nju667 7 7 (c) contrast adjustment by the evr function (c) contrast adjustment by the evr function the evr controls voltage of v the evr controls voltage of v reg reg by instruction and changes voltage of v by instruction and changes voltage of v 5 5 . . as result, lcd display contrast is adjusted by v as result, lcd display contrast is adjusted by v 5 5 . the evr selects a voltage of v . the evr selects a voltage of v reg reg in the following 201 in the following 201 conditions by setting 6bits data into the evr register. conditions by setting 6bits data into the evr register. in case of evr operation, t in case of evr operation, t 1 1 terminal and t terminal and t 2 2 require to set couples of value as (l,l),(l,h) and (h,l) excepting require to set couples of value as (l,l),(l,h) and (h,l) excepting for (h,h) and the internal power supply must turn on by instruction. for (h,h) and the internal power supply must turn on by instruction. (37)h to (4f)h available for use. if keeping 3% precision set evr over (4f)h. (37)h to (4f)h available for use. if keeping 3% precision set evr over (4f)h. min.(4f)h max.(ff)h adjustable range 6.2 - - - - - - - - - - - - - - - - - - - 15.0 [v] step voltagre 50 [mv] * in case of v * in case of v dd dd =3v =3v adjustable range of the lcd driving voltage by evr function adjustable range of the lcd driving voltage by evr function the adjustable range is decided by the power supply voltage v the adjustable range is decided by the power supply voltage v dd dd and the ratio of external resistors and the ratio of external resistors ra and rb. ra and rb. [ design example for the adjustable range / reference ] [ design example for the adjustable range / reference ] - condition v - condition v dd dd =3.0v, v =3.0v, v ss ss =0v =0v ra=1m ra=1m w w , rb=4m , rb=4m w w ( ra:rb=1:4 ) ( ra:rb=1:4 ) the adjustable range and the step voltage are calculated as follows in the above condition. the adjustable range and the step voltage are calculated as follows in the above condition. in case of setting (4f) in case of setting (4f) h h in the evr register, in the evr register, v v lcd lcd = ((ra+rb)/ra)v = ((ra+rb)/ra)v reg reg = (5/1) x [(100/300) x 3.0] = (5/1) x [(100/300) x 3.0] = 6.2v = 6.2v in case of setting (ff) in case of setting (ff) h h in the evr register, in the evr register, v v lcd lcd = ((ra+rb)/ra)v = ((ra+rb)/ra)v reg reg = (5/1) x [(300/300) x 3.0] = (5/1) x [(300/300) x 3.0] = 15.0v = 15.0v evr register v reg [v] v lcd : : : low : : : : : : : : : (4f) h (0,1,0,0,1,1,1,1) (124/300) x (v dd -v ss ) : : : : : : (fd) h (1,1,1,1,1,1,0,1) (298/300) x (v dd -v ss ) (fe) h (1,1,1,1,1,1,1,0) (299/300) x (v dd -v ss ) (ff) h (1,1,1,1,1,1,1,1) (300/300) x (v dd -v ss ) high
nju667 nju667 7 7 t.b.d. t.b.d. *) the v *) the v lcd lcd operating temperature. please refer to the following graphs. operating temperature. please refer to the following graphs. (conditions) v (conditions) v dd dd = 3v = 3v ra=1m ra=1m w w , rb=4m , rb=4m w w ( ra:rb = 1:4 ) ( ra:rb = 1:4 ) five times voltage five times voltage vlcd vs. temperature (typical performance) 0 2 4 6 8 10 12 14 16 -30 -20 -10 0 10 20 30 40 50 60 70 80 vlcd evr=(ff)h vlcd evr=(4f)h t.b.d t.b.d ta ( ta ( o o c) c) vlcd (v)
nju667 nju667 7 7 (d) lcd driving voltage generation circuits (d) lcd driving voltage generation circuits the lcd driving bias voltage of v the lcd driving bias voltage of v 1 1 ,v ,v 2 2 ,v ,v 3 3 ,v ,v 4 4 are generated internally by dividing the v are generated internally by dividing the v 5 5 voltage with the voltage with the internal bleeder resistance. and it is supplied to the lcd driving circuits after the impedance conversion with internal bleeder resistance. and it is supplied to the lcd driving circuits after the impedance conversion with voltage follower circuit. voltage follower circuit. as shown in fig. 4, five capacitors are required to connect to each lcd driving voltage terminal for voltage as shown in fig. 4, five capacitors are required to connect to each lcd driving voltage terminal for voltage stabilizing. and the value of capacitors c5, c6, c7, c8 and c9 are determined depending on the actual lcd stabilizing. and the value of capacitors c5, c6, c7, c8 and c9 are determined depending on the actual lcd panel display evaluation. panel display evaluation. using the internal power supply using the external power supply using the internal power supply using the external power supply fig.4 fig.4 *1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. *1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. *2 following connection of v *2 following connection of v out out is required when external power supply using. is required when external power supply using. when v when v ss ss > v > v 5 5 --- v --- v out out =v =v 5 5 when v when v ss ss < v < v 5 5 --- v --- v out out =v =v ss ss v 1 v 2 v 3 v 4 v 5 v d d v r v o u t c 2 - c 2 + c 1 - c 1 + v s s c o u t r 3 r 2 r 1 c 1 c 2 v 5 + + + + + + + + c 5 c 6 c 7 c 8 c 9 c 3 c 4 + + c 3 - c 3 + c 4 - c 4 + e x t e r n a l v o l t a g e g e n e r a t o r v 1 v 2 v 3 v 4 v 5 v d d v r v o u t c 2 - c 2 + c 1 - c 1 + v s s v 5 c 3 - c 3 + c 4 - c 4 + cout to 1.0uf c1 to c4 to 1.0uf c5 to c9 0.1 to 0.47uf r1 2.0m w r2 0.5m w r3 2.5m w reference set up value reference set up value vlcd=vdd-v5 = 9.0 to 10.5v vlcd=vdd-v5 = 9.0 to 10.5v NJU6677 NJU6677 NJU6677 NJU6677
nju667 nju667 7 7 (5-1) interface type selection (5-1) interface type selection NJU6677 interfaces with mpu by 8-bit bidirectional data bus (d NJU6677 interfaces with mpu by 8-bit bidirectional data bus (d 7 7 to d to d 0 0 ) or serial (si:d ) or serial (si:d 7 7 ). the 8 bit parallel or ). the 8 bit parallel or serial interface is determined by a condition of the p/s terminal connecting to "h" or "l" level as shown in serial interface is determined by a condition of the p/s terminal connecting to "h" or "l" level as shown in table 5. in case of the serial interface, status and ram data read out operation is impossible. table 5. in case of the serial interface, status and ram data read out operation is impossible. (5) mpu interface (5) mpu interface table 5 table 5 the NJU6677 interfaces to 68 or 80 type mpu directly when the parallel interface (p/s="h") is selected. the NJU6677 interfaces to 68 or 80 type mpu directly when the parallel interface (p/s="h") is selected. 68 type mpu or 80 is determined by the condition of sel68 terminal connecting to "h" or "l" as shown in 68 type mpu or 80 is determined by the condition of sel68 terminal connecting to "h" or "l" as shown in table 6. table 6. (5-2) parallel interface (5-2) parallel interface table 6 table 6 (5-3) discrimination of data bus signal (5-3) discrimination of data bus signal c s d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 3 6 4 1 0 2 1 7 5 8 9 s i s c l a 0 p/s type cs a0 rd wr sel68 d 7 d 6 d 0 to d 5 h parallel cs a0 rd wr sel68 d 7 d 6 d 0 to d 5 l serial cs a0 - - - si scl hi-z sel68 type cs a0 rd wr d 0 to d 7 h 68 type mpu cs a0 e r/w d 0 to d 7 l 80 type mpu cs a0 rd wr d 0 to d 7 the NJU6677 discriminates the mean of signal on the data bus by the combination of a0, e, r/w, and the NJU6677 discriminates the mean of signal on the data bus by the combination of a0, e, r/w, and (rd,wr) signals as shown in table 7. (rd,wr) signals as shown in table 7. table 7 table 7 common 68 type 80 type function a0 r/w rd wr 1 1 0 1 read display data 1 0 1 0 write display data 0 1 0 1 status read 0 0 1 0 write into the register(instruction) (5-4) serial interface.(p/s="l") (5-4) serial interface.(p/s="l") serial interface circuits consist of 8 bits shift register and 3 bits counter. si and scl input are activated when serial interface circuits consist of 8 bits shift register and 3 bits counter. si and scl input are activated when the chip select terminal cs set to "l"and p/s terminal set to "l". the 8 bits shift register and 3 bits counter are the chip select terminal cs set to "l"and p/s terminal set to "l". the 8 bits shift register and 3 bits counter are reset to the initial condition when the chip is not selected. the data input from si terminal is msb first like as reset to the initial condition when the chip is not selected. the data input from si terminal is msb first like as the order of d the order of d 7 7 ,d ,d 6 6 ,- - - - d ,- - - - d 0, 0, and the data are entered into the shift register synchronizing with the rise edge of and the data are entered into the shift register synchronizing with the rise edge of the serial clock scl. the data in the shift register are converted to parallel data at the 8th serial clock rise the serial clock scl. the data in the shift register are converted to parallel data at the 8th serial clock rise edge input. discrimination of the display data or instruction of the serial input data is executed by the condi- edge input. discrimination of the display data or instruction of the serial input data is executed by the condi- tion of a0 at the 8th serial clock rise edge. a0="h" is display data and a0="l" is instruction. when res tion of a0 at the 8th serial clock rise edge. a0="h" is display data and a0="l" is instruction. when res terminal becomes "l" or cs terminal becomes "h" before 8th serial clock rise edge, NJU6677 recognizes terminal becomes "l" or cs terminal becomes "h" before 8th serial clock rise edge, NJU6677 recognizes them as a instruction data incorrectly. therefore a unit of serial data must be structured by 8-bit. the time them as a instruction data incorrectly. therefore a unit of serial data must be structured by 8-bit. the time chart for the serial interface is shown in fig. 5. to avoid the noise trouble, the short wiring is required for the chart for the serial interface is shown in fig. 5. to avoid the noise trouble, the short wiring is required for the scl input. scl input. note) the read out function, such as the status or ram data read out, is not supported in this serial interface note) the read out function, such as the status or ram data read out, is not supported in this serial interface . . fig. 5 fig. 5
nju667 nju667 7 7 (5-5) access to the display data ram and internal register. (5-5) access to the display data ram and internal register. the NJU6677 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus the NJU6677 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus to adjust the operation frequency between mpu and the display data ram or internal register. to adjust the operation frequency between mpu and the display data ram or internal register. for example, when the mpu reads out the data from the display data ram, the read out data in the data read for example, when the mpu reads out the data from the display data ram, the read out data in the data read cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the next data read cycle. when the mpu writes the data into the display data ram, the data is held in the bus- next data read cycle. when the mpu writes the data into the display data ram, the data is held in the bus- holder, then it is written into the display data ram by the next data write cycle. holder, then it is written into the display data ram by the next data write cycle. therefore high speed data transmission between mpu and NJU6677 is available because of it is not limited by therefore high speed data transmission between mpu and NJU6677 is available because of it is not limited by the t the t acc acc and t and t ds ds as display data ram access time and is limited by the system cycle time (r) or (w). as display data ram access time and is limited by the system cycle time (r) or (w). if the cycle time is not be kept in the mpu operation, nop should be inserted to the system instead of the if the cycle time is not be kept in the mpu operation, nop should be inserted to the system instead of the waiting operation. waiting operation. the read out operation does not read out the data in the pointed address just after the address set operation. the read out operation does not read out the data in the pointed address just after the address set operation. and second read out operation can read out the data correctly from the pointed address. and second read out operation can read out the data correctly from the pointed address. therefore, one dummy read operation is required after address setting or write cycle as shown in fig. 6. therefore, one dummy read operation is required after address setting or write cycle as shown in fig. 6. w r d a t a i / o b u f f e r w r m p u i n t e r n a l t i m i n g n n + 1 n + 2 n + 3 n n + 1 n + 2 n + 3 w r d a t a i / o b u f f e r w r m p u i n t e r n a l t i m i n g r d n n n n + 1 a d d r e s s s e t n d u m m y r e a d d a t a r e a d n d a t a r e a d n + 1 r d c o l u m n a d d r e s s n n + 1 n + 2 n n n + 1 n + 2 write operation write operation read operation read operation fig.6 fig.6 (5-6) chip select (5-6) chip select cs is chip select terminal. in case of cs="l", the interface with mpu is available. in case of cs=?h?, the d cs is chip select terminal. in case of cs="l", the interface with mpu is available. in case of cs=?h?, the d 0 0 to d to d 7 7 are high impedance and a0, rd, wr, d are high impedance and a0, rd, wr, d 7 7 (si) and d (si) and d 6 6 (scl) inputs are ignored. if the serial interface is (scl) inputs are ignored. if the serial interface is selected when cs=?h?,the shift register and the counter are reset. however, the reset is always operated in selected when cs=?h?,the shift register and the counter are reset. however, the reset is always operated in any conditions of cs. any conditions of cs.
NJU6677 NJU6677 p a r a m e t e r symbol r a t i n g s unit supply voltage (1) v dd -0.3 to +5.0 v supply voltage (2) v 5 v dd -18.0 to v dd +0.3 v supply voltage (3) v 1 to v 4 v 5 to v dd +0.3 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +80 c storage temperature t stg -55 to +125 (chip) c -55 to +100 (tcp) absolute maximum ratings absolute maximum ratings (ta=25 (ta=25 c) c) note 1) if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. note 1) if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. using the lsi within electrical characteristics is strongly recommended for normal operation. use using the lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause malfunction and poor reliability. beyond the electric characteristics conditions will cause malfunction and poor reliability. note 2) all voltage values are specified as v note 2) all voltage values are specified as v ss ss =0 v. =0 v. note 3) the relation : v note 3) the relation : v dd dd > v > v 1 1 > v > v 2 2 > v > v 3 3 > v > v 4 4 > v > v 5 5 ; v ; v dd dd > v > v ss ss > v > v out out must be maintained. must be maintained. note 4) decoupling capacitor should be connected between v note 4) decoupling capacitor should be connected between v dd dd and v and v ss ss due to the stabilized operation for due to the stabilized operation for the voltage converter. the voltage converter. p a r a m e t e symbol c o n d i t i o n s min. typ. max. unit note operating voltage(1) v dd 2.4 3.6 v 5 operatingvoltage(2) v 5 v dd -18.0 v dd -6.0 v v 1 ,v 2 v lcd = v dd -v 5 vdd-0.5vlcd v dd v 3 ,v 4 v 5 vdd-0.5vlcd input voltage high level v ihc1 d 0 ...d 7 ,a0, cs,res,rd,wr,sel68, p/s terminals 0.8v dd v dd v low level v ilc1 v ss 0.2v dd v output voltage high level v ohc11 d 0 ...d 7 terminals i oh =-0.5ma 0.8v dd v dd v low level v olc11 i ol = 0.5ma v ss 0.2v dd v input leakage current i lio all input terminals - 1.0 1.0 ua 6 driver on-resistance r on1 ta=25 c v lcd =15.0v 2.0 3.0 k w 7 r on2 v lcd =8.0v 3.0 4.5 stand-by current i ddq during power save mode t.b.d. t.b.d. ua 8 operating current i dd12 display v lcd =12.0v t.b.d. t.b.d. ua i dd21 accessing f cyc =200khz t.b.d. t.b.d. 9 electrical characteristics (1) (vdd=2.7v to 3.3v, vss=0v, ta=-30 to +80 electrical characteristics (1) (vdd=2.7v to 3.3v, vss=0v, ta=-30 to +80 c c ) )
NJU6677 NJU6677 p a r a m e t e r symbol c o n d i t i o n s min typ max unit note input terminal capacitance c in a0,cs,res,rd,wr,sel68, p/s,t1,t2,d 0 ...d 7 ta=25 c 10 pf oscillation frequency f osc ta=25 c t.b.d. khz voltage booster output volt. v out1 v ss -vout, 5-time voltage booster, v dd =3v vdd-15.0 vdd-14.5 v on-resistance r tri v dd =3v;c1-c4,c out =4.7uf 5-time voltage booster t.b.d. w adjustment range of lcd driving volt. v out2 voltage booster circuit "off" v dd -18.0v v dd -6.0v v 10 voltage follower v 5 voltage adjustment circuit "off" v dd -18.0v v dd -6.0v v operating current i out1 v dd =3v, v lcd =12v com/seg terminals open no access display checkered pattern t.b.d. t.b.d. ua 11 i out2 t.b.d. t.b.d. i out3 t.b.d. t.b.d. voltage reg. v reg% v dd =3v,ta=25 c v reg =4f to ff h t.b.d. % note 5) NJU6677 can operate wide operating range, but it is not guarantee immediate voltage changing during note 5) NJU6677 can operate wide operating range, but it is not guarantee immediate voltage changing during the accessing of the mpu. the accessing of the mpu. note 6) apply to the high-impedance state of the d note 6) apply to the high-impedance state of the d 0 0 to d to d 7 7 terminals. terminals. note 7) r note 7) r on on is the resistance values between power supply terminals(v is the resistance values between power supply terminals(v 1 1 , v , v 2 2 , v , v 3 3 , v , v 4 4 ) and each output ) and each output terminals of common and segment supplied by 0.1v. this is specified within the range of supply terminals of common and segment supplied by 0.1v. this is specified within the range of supply voltage (2). voltage (2). note 8,9,11) apply to current after "lcd driving voltage set". note 8,9,11) apply to current after "lcd driving voltage set". note 8) apply to the external display clock operation in no access from the mpu and no use internal power note 8) apply to the external display clock operation in no access from the mpu and no use internal power supply circuits. supply circuits. note 9) apply to the condition of cyclic (tcyc) inverted data input continuously in no use internal power supply note 9) apply to the condition of cyclic (tcyc) inverted data input continuously in no use internal power supply circuits. the operating current during the accessing is proportionate to the access frequency. in the no circuits. the operating current during the accessing is proportionate to the access frequency. in the no accessing period, it is as same as i accessing period, it is as same as i dd01 dd01 . . note 10) lcd driving voltage v note 10) lcd driving voltage v 5 5 can be adjusted within the voltage follower operating range. can be adjusted within the voltage follower operating range. note 11) each operating current of voltage supply circuits block is specified under below table conditions. note 11) each operating current of voltage supply circuits block is specified under below table conditions. symbol status operating condition external voltage supply (input terminal) t 1 t 2 internal oscillator voltage booster voltage adjustment voltage follower i out1 l * validity validity validity validity unuse i out2 h l validity invalidity validity validity use(v out ) i out3 h h validity invalidity invalidity validity use(v out ,v 5 ) (* = don?t care) (* = don?t care)
NJU6677 NJU6677 a n j u 6 6 7 7 c 1 + c 1 - c 2 + c 2 - + + + v s s v d d v r v 5 t 1 t 2 v o u t c 3 + c 3 - c 4 + c 4 - + + a n j u 6 6 7 7 c 1 + c 1 - c 2 + c 2 - v s s v d d v r v 5 t 1 t 2 v o u t c 3 + c 3 - c 4 + c 4 - a n j u 6 6 7 7 c 1 + c 1 - c 2 + c 2 - v s s v d d v r v 5 t 1 t 2 v o u t c 3 + c 3 - c 4 + c 4 - :i :i out1 out1 :i :i out2 out2 measurement block diagram measurement block diagram :i :i out3 out3 note 12) specified from the rising edge of res to finish the internal circuit reset. note 12) specified from the rising edge of res to finish the internal circuit reset. note 13) specified minimum pulse width of res signal. over than t note 13) specified minimum pulse width of res signal. over than t rw rw "l" input should be required for correct "l" input should be required for correct reset operation. reset operation. electrical characteristics (2) (vdd=2.7v to 3.3v, vss=0v, ta=-30 to +80 electrical characteristics (2) (vdd=2.7v to 3.3v, vss=0v, ta=-30 to +80 c c ) ) p a r a m e t e r symb- ol c o n d i t i o n s min typ max unit note reset tim e t r res terminal 1.0 us 12 reset "l" level pulse width t rw res terminal 10 us 13
NJU6677 NJU6677 bus timing characteristics bus timing characteristics - read/write operation sequence (80 type mpu) - read/write operation sequence (80 type mpu) a 0 , c s d 0 t o d 7 ( w r i t e ) w r , r d d 0 t o d 7 ( r e a d ) t c y c 8 t a w 8 t c c h t c c l t a h 8 t d s 8 t d h 8 t a c c t c h 8 t f t r (v (v dd dd = = 2.4v to 3.6v 2.4v to 3.6v ,ta= ,ta= -30 to +80 -30 to +80 c c ) ) p a r a m e t e r symbol min. typ. max. condition unit address hold time a0,cs terminals t ah8 10 ns address set up time t aw8 0 ns system cycle time wr wr,rd terminals t cyc8 (w) 220 ns rd t cyc8 (r) 350 ns control pulse width wr,"l" t ccl (w) 50 ns rd,"l" t ccl (r) 200 ns wr"h" t cch(w) 160 ns rd"- h" t cch (r) 160 ns data set up time d 0 to d 7 terminals t ds8 35 ns data hold time t dh8 15 ns rd access time t acc8 120 cl=100pf ns output disable time t ch8 15 ns rise time, fall time cs, wr, rd, a0, d0 to d7 terminals t r ,t f 15 ns note 14) rise time (t note 14) rise time (t r r ) and fall time (t ) and fall time (t f f ) of input signal should be less than 15ns. ) of input signal should be less than 15ns. note 15) each timing is specified based on 0.2xv note 15) each timing is specified based on 0.2xv dd dd and 0.8xv and 0.8xv dd dd . .
NJU6677 NJU6677 - read/write operation sequence (68 type mpu) - read/write operation sequence (68 type mpu) a 0 , c s d 0 t o d 7 ( w r i t e ) r / w d 0 t o d 7 ( r e a d ) t c y c 6 t a w 6 t e w h t a h 6 t d s 6 t d h 6 t a c c 6 t o h 6 t f t r e t e w l p a r a m e t e r symbol min. typ. max. condition unit address hold time a0,cs,r/w terminals t ah6 10 ns address set up time t aw6 0 ns system cycle time(w) t cyc6 (w) 220 ns system cycle time(r) t cyc 6(r) 350 ns enable pulse width read"h" e terminal t ewh 200 ns write"h" 50 ns read"l" t ewl 160 ns write"h" 160 ns data set up time d 0 to d 7 terminals t ds6 35 ns data hold time t dh6 15 ns access time t acc6 150 cl=100pf ns output disable time t oh6 20 ns rise time, fall tim e a0, cs, r/w, e, d 0 to d 7 terminals t r ,t f 15 ns note 16) t note 16) t cyc6 cyc6 indicates the e signal cycle during the cs activation period. the system cycle time must be indicates the e signal cycle during the cs activation period. the system cycle time must be required after cs becomes active. required after cs becomes active. note 17) rise time (t note 17) rise time (t r r ) and fall time (t ) and fall time (t f f ) of input signal should be less than 15ns. ) of input signal should be less than 15ns. note 18) each timing is specified based on 0.2xv note 18) each timing is specified based on 0.2xv dd dd and 0.8xv and 0.8xv dd dd . . (v (v dd dd = = 2.4v to 3.6v 2.4v to 3.6v ,ta= ,ta= -30 to +80 -30 to +80 c c ) )
NJU6677 NJU6677 scl scl scl 8th clock scl 8th clock scl 1st clock scl 1st clock scl"l"pulse width scl"l"pulse width (between the (between the instruction and next) instruction and next) instruction n instruction n instruction n+1 instruction n+1 450 ns 450 ns - write operation sequence (serial interface) - write operation sequence (serial interface) c s s c l a 0 s i t s c y c t s a s t s h w t s a h t c s h t s l w t s d s t s d h t f t r t c s s p a r a m e t e r symbol min. typ. max. condition unit serial clock cycle scl terminal t scyc 60 ns scl "h" pulse width t shw 30 ns scl "l" pulse width t slw 30 ns address set up time a0 terminal t sas 0 ns address hold time t sah 150 ns data set up time si terminal t sds 25 ns data hold time t sdh 10 ns cs-scl time cs terminal t css 10 ns t csh 300 ns rise time, fall tim e scl, a0, cs, si terminals t r ,t f 15 ns note 19) rise time (t note 19) rise time (t r r ) and fall time (t ) and fall time (t f f ) of input signal should be less than 15ns. ) of input signal should be less than 15ns. note 20) each timing is specified based on 0.2xv note 20) each timing is specified based on 0.2xv dd dd and 0.8xv and 0.8xv dd dd . . note 21) in case of instruction set continuously, it is required to wait more than 450ns between the instruction note 21) in case of instruction set continuously, it is required to wait more than 450ns between the instruction and next as follows. and next as follows. (v (v dd dd = = 2.4v to 3.6v 2.4v to 3.6v ,ta= ,ta= -30 to +80 -30 to +80 c c ) )
NJU6677 NJU6677 lcd driving waveform lcd driving waveform v d d v 1 v 2 v 3 v 4 v 5 c o m 1 c o m 0 c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 c o m 7 c o m 8 c o m 9 c o m 1 0 c o m 1 1 c o m 1 2 c o m 1 3 c o m 1 4 s e g 1 s e g 0 c o m 1 5 s e g 1 s e g 2 s e g 3 s e g 4 1 2 3 4 8 6 1 2 3 4 5 c o m 2 c o m 0 s e g 0 0 0 v d d v s s c o m 0 - s e g 0 v d d - v 1 - v 2 - v 3 - v 4 - v 5 v 5 v 4 v 3 v 2 v 1 c o m 0 - s e g 1 v d d - v 1 - v 2 - v 3 - v 4 - v 5 v 5 v 4 v 3 v 2 v 1 f r 8 7 8 6 8 7 v d d v 1 v 2 v 3 v 4 v 5 v d d v 1 v 2 v 3 v 4 v 5 v d d v 1 v 2 v 3 v 4 v 5 v d d v 1 v 2 v 3 v 4 v 5 fig.7 fig.7
NJU6677 NJU6677 application circuit application circuit - microprocessor interface example - microprocessor interface example the NJU6677 interfaces to 80 type or 68 type mpu directly. the NJU6677 interfaces to 80 type or 68 type mpu directly. and the serial interface also communicate with mpu. and the serial interface also communicate with mpu. m p u a 0 a 0 t o a 7 r e s a 0 c s r e s r e s e t s e l 6 8 p / s v c c g n d n j u 6 6 7 7 v s s v d d a 0 a 0 t o a 1 5 v m a d 0 t o d 7 e r / w r e s a 0 c s d 0 t o d 7 e r / w r e s r e s e t s e l 6 8 p / s g n d a 0 a 1 t o a 7 i o r q d 0 t o d 7 r d w r r e s a 0 c s s i s c l r e s r e s e t s e l 6 8 p / s g n d p o r t 1 p o r t 2 v d d o r g n d d 0 t o d 7 r d w r v c c v d d v s s v c c v d d v s s m p u d e c o d e r n j u 6 6 7 7 m p u d e c o d e r n j u 6 6 7 7 d e c o d e r - - 80 type mpu 80 type mpu - - 68 type mpu 68 type mpu - - serial interface serial interface
NJU6677 NJU6677 l c d p a n e l ( 8 8 x 1 3 2 ) n j u 6 6 7 7 c 4 4 c 8 7 s 0 c 0 c 4 3 s 1 3 1 b o t t o m v i e w lcd panel interface example lcd panel interface example caution caution the specifications on this databook are only the specifications on this databook are only given for information , without any guarantee given for information , without any guarantee as regards either mistakes or omissions. the as regards either mistakes or omissions. the application circuits in this databook are application circuits in this databook are described only to show representative usages described only to show representative usages of the product and not intended for the of the product and not intended for the guarantee or permission of any right including guarantee or permission of any right including the industrial rights. the industrial rights.

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